{
  "schema_version": "touchdown.cxmt-memory-chapter-evidence.v1",
  "chapter_id": "cxmt-ipo-hbm-proof-gates",
  "title": "CXMT and the memory wall: from one DRAM cell to a qualified HBM system",
  "updated_at": "2026-07-27",
  "publication_state": "source_backed_public_chapter",
  "run_id": null,
  "touchdown_hbm_run_captured": false,
  "editorial_position": "Compare each product on separate evidence tracks: matched workload performance, confirmed supplier relationships, qualification, production volume, and dated readiness milestones. Improvement on one track does not establish another.",
  "evidence_states": {
    "official": "Published by CXMT or a standards body.",
    "reported": "Reported by Reuters or another named publication and not independently published as a CXMT product specification.",
    "teardown": "Observed by an independent physical teardown or process analysis; not a CXMT product specification.",
    "patent": "Published patent application or patent. It signals research direction, not product implementation or qualification.",
    "derived": "Arithmetic or first-principles explanation derived from named public inputs.",
    "unknown": "No adequate public receipt was identified for this field."
  },
  "claims": [
    {
      "claim_id": "cxmt-company-scope",
      "state": "official",
      "claim": "CXMT was founded in 2016 and specializes in DRAM design, manufacturing, sales, and research and development.",
      "source": "https://www.cxmt.com/en/about.html"
    },
    {
      "claim_id": "cxmt-ddr5-portfolio",
      "state": "official",
      "claim": "CXMT lists DDR5 dies at up to 8000 Mbps in 16Gb and 24Gb densities, with DDR5 modules for server, workstation, desktop, and laptop applications.",
      "source": "https://www.cxmt.com/en/product.html"
    },
    {
      "claim_id": "cxmt-ddr5-module-forms",
      "state": "official",
      "claim": "CXMT publicly showed UDIMM, SODIMM, CUDIMM, CSODIMM, RDIMM, MRDIMM, and TFF MRDIMM products in November 2025.",
      "source": "https://www.cxmt.com/en/news/info_20.html"
    },
    {
      "claim_id": "cxmt-lpddr5x-portfolio",
      "state": "official",
      "claim": "CXMT lists LPDDR5X dies in 12Gb and 16Gb densities with speeds up to 10667 Mbps; 8533 and 9600 Mbps products entered mass production in May 2025, while 10667 Mbps entered customer sampling in October 2025.",
      "source": "https://www.cxmt.com/en/news/info_19.html"
    },
    {
      "claim_id": "cxmt-quality-system",
      "state": "official",
      "claim": "CXMT describes statistical process control, equipment data monitoring, parameter optimization, big-data yield improvement, outgoing quality control, full production history, reliability management, supplier audits, and multiple quality and continuity certifications.",
      "source": "https://www.cxmt.com/en/service.html"
    },
    {
      "claim_id": "cxmt-rd-system",
      "state": "official",
      "claim": "CXMT says approximately 80 percent of its personnel are in research, development, or technical roles and describes international licensing and research cooperation.",
      "source": "https://www.cxmt.com/en/innovation.html"
    },
    {
      "claim_id": "cxmt-public-catalog-hbm-boundary",
      "state": "official",
      "claim": "CXMT's current public product catalog lists DDR5, LPDDR5/LPDDR5X, DDR4, and LPDDR4X, but does not list a commercial HBM product.",
      "source": "https://www.cxmt.com/en/product.html"
    },
    {
      "claim_id": "cxmt-hbm3-target",
      "state": "reported",
      "claim": "Reuters reported in October 2025 that CXMT was targeting HBM3 mass production in 2026 and that sources associated the target with its G4 16nm DRAM generation.",
      "source": "https://www.reuters.com/world/asia-pacific/chipmaker-cxmt-plans-shanghai-listing-with-42-billion-valuation-sources-say-2025-10-21/"
    },
    {
      "claim_id": "cxmt-shanghai-packaging-facility",
      "state": "reported",
      "claim": "Reuters reported that CXMT was building an HBM back-end packaging facility in Shanghai with production targeted for late 2026.",
      "source": "https://www.reuters.com/world/asia-pacific/chinas-cxmt-eyes-42-billion-shanghai-listing-fund-dram-expansion-2025-12-31/"
    },
    {
      "claim_id": "cxmt-hbm-wafer-capacity-report",
      "state": "reported",
      "claim": "Reuters reported, citing sources, an initial HBM wafer output target of approximately 30000 wafers per month. This is not treated as a completed or qualified capacity receipt.",
      "source": "https://www.reuters.com/world/asia-pacific/chipmaker-cxmt-plans-shanghai-listing-with-42-billion-valuation-sources-say-2025-10-21/"
    },
    {
      "claim_id": "cxmt-g4-teardown",
      "state": "teardown",
      "claim": "TechInsights describes a process analysis of a CXMT G4 16Gb DDR5 die. Secondary reporting of that teardown estimates a 66.99 square millimeter die, 0.239 Gb per square millimeter bit density, and an approximately 16nm feature size.",
      "source": "https://www.techinsights.com/blog/cxmt-g4-16gb-ddr5-dram-process-analysis"
    },
    {
      "claim_id": "bis-hbm-controls",
      "state": "official",
      "claim": "The U.S. Commerce Department's December 2024 package added controls on high-bandwidth memory and specified semiconductor-manufacturing equipment. The transaction impact depends on the product, supplier, customer, end use, date, and license.",
      "source": "https://www.bis.gov/press-release/commerce-strengthens-export-controls-restrict-chinas-capability-produce-advanced-semiconductors-military"
    },
    {
      "claim_id": "asml-duv-license-boundary",
      "state": "official",
      "claim": "ASML stated in September 2024 that specified advanced immersion-DUV models require Dutch export licenses. The statement does not make every DUV system one categorically prohibited class.",
      "source": "https://www.asml.com/en/news/press-releases/2024/dutch-governments-updated-export-license-requirement"
    },
    {
      "claim_id": "duv-patterning-mechanism",
      "state": "derived",
      "claim": "At pitches below a single 193nm immersion-DUV exposure's practical resolution, manufacturers can split or multiply patterns across additional masks, deposition, etch, clean, inspection, and metrology steps. This extends scaling while increasing overlay, edge-placement, cycle-time, defect, capacity, yield, and cost pressure.",
      "source": "https://www.asml.com/en/technology/lithography-principles/rayleigh-criterion"
    },
    {
      "claim_id": "domestic-immersion-duv-initial-production",
      "state": "reported",
      "claim": "The Information, relayed by Reuters on July 27, 2026, reported initial production of China-developed immersion-DUV tools, with output targets of approximately five systems in 2026 and twenty in 2027. The report does not establish completed and accepted systems, a disclosed bill of materials, qualified production insertion, or high-volume chip manufacturing.",
      "source": "https://live.euronext.com/en/financial-news/china-begins-making-homegrown-duv-chipmaking-tools-information-reports"
    },
    {
      "claim_id": "hbm3-standard",
      "state": "official",
      "claim": "JEDEC's HBM3 standard defines data rates up to 6.4 Gb/s and bandwidth up to 819 GB/s per device, with 16 independent channels and two pseudo-channels per channel.",
      "source": "https://www.businesswire.com/news/home/20220127005320/en/JEDEC-Publishes-HBM3-Update-to-High-Bandwidth-Memory-HBM-Standard"
    },
    {
      "claim_id": "hbm4-standard",
      "state": "official",
      "claim": "JEDEC's HBM4 standard defines transfer speeds up to 8 Gb/s across a 2048-bit interface for up to 2 TB/s per stack and doubles the independent channel count to 32.",
      "source": "https://www.businesswire.com/news/home/20250416843598/en/JEDEC-and-Industry-Leaders-Collaborate-to-Release-JESD270-4-HBM4-Standard-Advancing-Bandwidth-Efficiency-and-Capacity-for-AI-and-HPC"
    },
    {
      "claim_id": "cxmt-stacked-memory-patent",
      "state": "patent",
      "claim": "EP4712722A1, assigned to CXMT, describes a memory chip, logic chip, chip-stacked structure, and conductive-via groups through a global signal region.",
      "source": "https://patents.google.com/patent/EP4712722A1/en"
    },
    {
      "claim_id": "cxmt-bonding-patent",
      "state": "patent",
      "claim": "WO2026081450A1, assigned to CXMT, describes a semiconductor structure with bonding pads at different depths and dielectric-layer openings.",
      "source": "https://patents.google.com/patent/WO2026081450A1/en"
    },
    {
      "claim_id": "cxmt-on-chip-controller-patent",
      "state": "patent",
      "claim": "CN121687150A, assigned to CXMT, describes a memory array, an on-chip controller, a memory controller, and parallel access to normal data and metadata regions.",
      "source": "https://patents.google.com/patent/CN121687150A/en"
    },
    {
      "claim_id": "cxmt-interchip-signaling-patent",
      "state": "patent",
      "claim": "US20260121660A1, assigned to CXMT, describes parallel-to-serial conversion, multi-level modulation, and a transmission path to another chip.",
      "source": "https://patents.google.com/patent/US20260121660A1/en"
    },
    {
      "claim_id": "ddr5-8000-derived-bandwidth",
      "state": "derived",
      "claim": "A 64-bit data path operating at 8000 megatransfers per second has a theoretical raw transfer ceiling of 64 GB/s: 64 bits times 8 billion transfers per second divided by 8 bits per byte. Actual system bandwidth depends on controller, channel count, traffic pattern, timing, refresh, and protocol overhead.",
      "source": "https://www.cxmt.com/en/product.html"
    },
    {
      "claim_id": "hbm3-derived-bandwidth",
      "state": "derived",
      "claim": "The HBM3 standard ceiling of 819.2 GB/s follows from 1024 data bits times 6.4 billion transfers per second divided by 8 bits per byte.",
      "source": "https://www.businesswire.com/news/home/20220127005320/en/JEDEC-Publishes-HBM3-Update-to-High-Bandwidth-Memory-HBM-Standard"
    },
    {
      "claim_id": "hbm4-derived-bandwidth",
      "state": "derived",
      "claim": "The HBM4 standard ceiling of 2048 GB/s follows from 2048 data bits times 8 billion transfers per second divided by 8 bits per byte.",
      "source": "https://www.businesswire.com/news/home/20250416843598/en/JEDEC-and-Industry-Leaders-Collaborate-to-Release-JESD270-4-HBM4-Standard-Advancing-Bandwidth-Efficiency-and-Capacity-for-AI-and-HPC"
    }
  ],
  "unknowns": [
    "Commercial CXMT HBM product name",
    "HBM generation and standard compliance",
    "Core-die process and die size",
    "Capacity per stack",
    "Stack height",
    "Per-pin data rate and interface width",
    "Base-die owner, process, and logic partition",
    "TSV and bonding process",
    "Known-good-die strategy",
    "Front-end die yield",
    "Stack and package yield",
    "Repair and redundancy coverage",
    "Package, interposer, bridge, or substrate",
    "Accelerator and memory-controller qualification",
    "Firmware and runtime support",
    "Thermal envelope and sustained bandwidth",
    "Reliability and shipment volume",
    "Measured workload performance",
    "Cost and energy per accepted AI task",
    "Production-qualified use of a China-developed immersion-DUV system at CXMT",
    "Country-of-origin distribution of the CXMT manufacturing and HBM chain",
    "China-developed immersion-DUV overlay, critical-dimension uniformity, throughput, uptime, service interval, electrical yield, and qualified production lots"
  ],
  "publication_boundary": "No patent, target date, financing event, conventional DRAM product, scanner production report, or independent teardown is presented as a qualified CXMT HBM product, complete qualified end-to-end supplier chain, or workload result."
}