{ "schema_version": "touchdown.china-ai-chip-memory-atlas.v2", "title": "China AI Chip & Memory Atlas", "updated_at": "2026-08-01", "scope": "Public evidence for Chinese AI accelerators, memory systems, packaging, interconnects, software, and production state. Version 2 adds source-normalized product families from the dated candidate ledger without inferring product-specific suppliers.", "editorial_position": "Compare each product on separate evidence tracks: matched workload performance, confirmed supplier relationships, qualification, production volume, and dated readiness milestones. Improvement on one track does not establish another.", "evidence_states": { "official": "Published by the company, a standards body, a regulator, or an official conference presentation.", "independent": "Observed in a teardown, reproducible third-party test, peer-reviewed work, or named qualification artifact.", "reported": "Published by a named news or industry source but not independently verified here.", "derived": "Arithmetic derived from named public inputs. It is not a measurement.", "unknown": "No adequate public evidence was found. The field stays blank." }, "comparison_rules": [ "Keep precision and sparsity conventions attached to every compute number.", "Separate peak memory bandwidth from sustained workload bandwidth.", "Separate per-chip, per-card, per-link, and aggregate-system interconnect numbers.", "A nominal process node is not a workload result.", "HBM-free describes a memory architecture; it does not prove that HBM has been replaced.", "Production readiness requires orderable hardware, qualified systems, software, reliability, and repeatable workload receipts." ], "discovery_sources": [ { "label": "tphuang DF1000 thread on X", "url": "https://x.com/tphuang/status/2081854933972799534", "use": "Research lead for the mature-node, HBM-free, memory-bandwidth, and interconnect comparison.", "boundary": "The post is not used as independent proof of DF1000 performance. Product fields are traced to company, industry, technical, or independent sources below." } ], "products": [ { "id": "dfsx-df1000", "company": "Shanghai DFSX", "product": "DF1000", "role": "Datacenter training and inference accelerator", "architecture": "Software-defined spatial/dataflow accelerator with DRAM vertically integrated over logic", "process": { "node_nm": 14, "node_class": "mature-node-class", "state": "reported" }, "compute": [ { "value": 520, "unit": "TFLOPS", "precision": "BF16", "scope": "peak, dense-versus-sparse undisclosed", "state": "reported" } ], "memory": { "strategy": "3d-near-memory", "hbm_free": true, "type": "DRAM, exact generation unknown", "capacity_gb": null, "peak_bandwidth_tb_s": 6.4, "bandwidth_scope": "company peak; raw/effective/internal/sustained scope unknown", "state": "reported" }, "interconnect": { "peak_gb_s": 900, "scope": "company-stated scale-up bandwidth; direction, ports, topology and payload rate unknown", "state": "reported" }, "package": { "description": "Company describes wafer-level DRAM-logic 3D hybrid bonding and an OAM 2.0 card", "state": "reported" }, "software": [ "CAAP", "driver", "runtime", "operator libraries", "distributed tools" ], "availability": { "state": "reported", "status": "Launched July 13, 2026; cards and systems shown; company claims functional validation and mass-production readiness; no public volume-shipment receipt" }, "independent_validation": "A peer-reviewed predecessor demonstrates the architectural direction, not DF1000 product specifications. No public DF1000 teardown or independent workload benchmark was found.", "sources": [ { "label": "DFSX product page", "url": "https://www.dfsx.com/products/ai-accelerator/df1000", "state": "official" }, { "label": "DFSX near-memory architecture", "url": "https://www.dfsx.com/technology/3d-near-memory-computing", "state": "official" }, { "label": "TrendForce China launch report", "url": "https://www.trendforce.cn/industry-news/semiconductors/20260714-6437.html", "state": "reported" }, { "label": "Independent architectural assessment", "url": "https://xenospectrum.com/en/dfsx-df1000-3d-dram-14nm/", "state": "independent" } ], "unknowns": [ "usable memory capacity", "DRAM vendor and generation", "sustained bandwidth", "card power", "die area", "stack yield", "latency", "RAS", "link topology", "software maturity", "customer qualification", "volume shipments" ], "entity_level": "datacenter_accelerator_family", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "Dataflow or spatial ASIC", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "huawei-ascend-910c", "company": "Huawei", "product": "Ascend 910C / Atlas 900 A3", "role": "Datacenter training and inference NPU", "architecture": "Tensor-centric Ascend architecture in a multi-die package", "process": { "node_nm": 7, "node_class": "advanced-constrained", "state": "independent", "note": "Sample-dependent. Teardowns found TSMC-fabricated 7 nm logic in examined units; reporting also describes SMIC N+2 revisions." }, "compute": [ { "value": 780, "unit": "TFLOPS", "precision": "BF16", "scope": "derived per chip from Huawei's 0.30 BF16 EFLOPS for 384 chips", "state": "derived" } ], "memory": { "strategy": "hbm", "hbm_free": false, "type": "HBM2E", "capacity_gb": 128, "peak_bandwidth_tb_s": 3.125, "bandwidth_scope": "derived from Huawei aggregate system figure; not a direct chip datasheet", "state": "derived" }, "interconnect": { "peak_gb_s": 270, "scope": "reported one-way internal dual-die link; Atlas 900 A3 scales through UnifiedBus/SuperPoD", "state": "reported" }, "package": { "description": "Multi-die accelerator with HBM2E; sampled component provenance varies", "state": "independent" }, "software": [ "CANN", "AscendCL", "MindSpore", "PyTorch adapters", "HCCL", "MindIE" ], "availability": { "state": "official", "status": "In production and deployed in Atlas 900 A3 systems; Huawei reported more than 300 systems at over 20 customers by September 2025" }, "independent_validation": "TechInsights teardowns establish physical silicon and HBM in sampled packages. Public neutral workload-efficiency data remain limited.", "sources": [ { "label": "Huawei Atlas 900 A3", "url": "https://e.huawei.com/cn/products/computing/ascend/atlas-900-a3-superpod", "state": "official" }, { "label": "Huawei deployment statement", "url": "https://www.huawei.com/cn/news/2025/9/hc-superpod-innovation", "state": "official" }, { "label": "TechInsights findings reported by DigiTimes", "url": "https://www.digitimes.com/news/a20251005PD200/huawei-ascend-tsmc-techinsights-samsung.html", "state": "independent" } ], "unknowns": [ "production mix by foundry and revision", "direct per-chip compute table", "exact link topology", "measured workload efficiency", "system power per accepted task" ], "entity_level": "datacenter_accelerator_and_system_family", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "NPU / tensor ASIC", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "huawei-ascend-950pr", "company": "Huawei", "product": "Ascend 950PR", "role": "Prefill and recommendation NPU", "architecture": "Prefill-optimized Ascend accelerator with Huawei-defined HiBL memory", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": 1, "unit": "PFLOPS", "precision": "FP8", "scope": "roadmap target", "state": "official" }, { "value": 2, "unit": "PFLOPS", "precision": "FP4", "scope": "roadmap target", "state": "official" } ], "memory": { "strategy": "hbm-class", "hbm_free": false, "type": "HiBL 1.0", "capacity_gb": 128, "peak_bandwidth_tb_s": 1.6, "bandwidth_scope": "official roadmap; reported launched configurations differ", "state": "official" }, "interconnect": { "peak_gb_s": 2000, "scope": "company-claimed LingQu scale-up bandwidth", "state": "official" }, "package": { "description": "Exact die count and memory/package cross-section unknown", "state": "unknown" }, "software": [ "CANN", "MindIE", "HCCL", "LingQu", "CUDA migration tools" ], "availability": { "state": "reported", "status": "Officially announced; reported in Atlas 350 configurations in 2026; independent teardown and customer benchmark not found" }, "independent_validation": "None found for final silicon specifications or end-to-end workload performance.", "sources": [ { "label": "Huawei roadmap", "url": "https://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech", "state": "official" } ], "unknowns": [ "process node", "power", "die count", "package", "memory provenance", "final capacity and bandwidth by SKU", "effective bandwidth", "customer benchmark" ], "entity_level": "datacenter_accelerator_family", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "NPU / tensor ASIC", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "huawei-ascend-950dt", "company": "Huawei", "product": "Ascend 950DT", "role": "Decode and training NPU", "architecture": "Decode/training-optimized Ascend accelerator with higher-bandwidth HiZQ memory", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": 1, "unit": "PFLOPS", "precision": "FP8", "scope": "roadmap/system-derived", "state": "derived" }, { "value": 2, "unit": "PFLOPS", "precision": "FP4", "scope": "roadmap/system-derived", "state": "derived" } ], "memory": { "strategy": "hbm-class", "hbm_free": false, "type": "HiZQ 2.0", "capacity_gb": 144, "peak_bandwidth_tb_s": 4, "bandwidth_scope": "official roadmap target", "state": "official" }, "interconnect": { "peak_gb_s": 2000, "scope": "company-claimed LingQu scale-up bandwidth", "state": "official" }, "package": { "description": "Unknown", "state": "unknown" }, "software": [ "CANN", "MindIE", "HCCL", "LingQu" ], "availability": { "state": "official", "status": "Roadmap product planned for later 2026; schedule reports vary; no independent silicon measurement found" }, "independent_validation": "None found for final silicon.", "sources": [ { "label": "Huawei roadmap", "url": "https://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech", "state": "official" } ], "unknowns": [ "process node", "package", "power", "silicon state", "shipment volume", "benchmark data", "final schedule" ], "entity_level": "datacenter_accelerator_family", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "NPU / tensor ASIC", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "cambricon-mlu370", "company": "Cambricon", "product": "MLU370 family", "role": "Datacenter inference and training accelerator", "architecture": "MLUv03 clusters with compute cores, memory core, and shared SRAM", "process": { "node_nm": 7, "node_class": "advanced-constrained", "state": "reported", "note": "Commonly reported; not established in the public manual used here." }, "compute": [ { "value": null, "unit": null, "precision": "FP32/TF32/FP16/BF16/INT8 supported", "scope": "authoritative rates vary by board and remain incomplete", "state": "unknown" } ], "memory": { "strategy": "lpddr", "hbm_free": true, "type": "LPDDR5", "capacity_gb": 48, "peak_bandwidth_tb_s": 0.3072, "bandwidth_scope": "MLU370-M8 manual", "state": "independent" }, "interconnect": { "peak_gb_s": 200, "scope": "aggregate bidirectional across four MLU-Link ports on M8", "state": "independent" }, "package": { "description": "PCIe board; no HBM/interposer", "state": "independent" }, "software": [ "Neuware", "CNRT", "CNDrv", "CNCL", "MagicMind", "BANG C/C++" ], "availability": { "state": "independent", "status": "Long-standing production hardware with public manuals and academic workload use" }, "independent_validation": "An academic MLU370-X4 implementation measured a 27% TPS improvement from LPDDR-aware allocation. That is a memory-management result, not a cross-vendor benchmark.", "sources": [ { "label": "FCC-hosted MLU370-M8 manual", "url": "https://fcc.report/FCC-ID/2ARVF-MLU370-M8/5528126.pdf", "state": "independent" }, { "label": "Cambricon documentation", "url": "https://developer.cambricon.com/index/document/index/classid/3.html", "state": "official" }, { "label": "ODMA paper", "url": "https://arxiv.org/abs/2512.09427", "state": "independent" } ], "unknowns": [ "verified process node and foundry", "package details", "complete compute table", "sustained bandwidth", "multi-card topology beyond local bridges" ], "entity_level": "datacenter_accelerator_family", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "NPU / tensor ASIC", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "cambricon-mlu590-690", "company": "Cambricon", "product": "MLU590 / MLU690", "role": "Newer cloud training and inference accelerators", "architecture": "Public microarchitecture detail incomplete", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "unknown", "state": "unknown" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "unknown", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "MLU590 appears in current CNCL/MLUDirect locality documentation; bandwidth unknown", "state": "official" }, "package": { "description": "Unknown", "state": "unknown" }, "software": [ "Neuware", "CNCL", "MLUDirect" ], "availability": { "state": "official", "status": "MLU590 is recognized by current SDK documentation; this alone does not prove volume shipment. Reliable public MLU690 specifications were not found." }, "independent_validation": "None found.", "sources": [ { "label": "Cambricon developer documentation", "url": "https://developer.cambricon.com/", "state": "official" } ], "unknowns": [ "process", "compute", "memory", "package", "interconnect bandwidth", "power", "availability", "MLU690 product state" ], "entity_level": "datacenter_accelerator_family", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "NPU / tensor ASIC", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "biren-br100", "company": "Biren Technology", "product": "BR100 / BR104", "role": "Datacenter GPGPU for training and inference", "architecture": "General vector processor plus 2.5D GEMM engine, C-Warp mode, large SRAM, multicast, and near-memory features", "process": { "node_nm": 7, "node_class": "advanced-constrained", "state": "official" }, "compute": [ { "value": 1, "unit": "PFLOPS", "precision": "BF16", "scope": "BR100 peak company claim", "state": "official" }, { "value": 256, "unit": "TFLOPS", "precision": "FP32", "scope": "BR100 peak company claim", "state": "official" }, { "value": 2, "unit": "POPS", "precision": "INT8", "scope": "BR100 peak company claim", "state": "official" } ], "memory": { "strategy": "hbm", "hbm_free": false, "type": "HBM2E", "capacity_gb": 64, "peak_bandwidth_tb_s": 2.3, "bandwidth_scope": "reported BR100 peak", "state": "reported" }, "interconnect": { "peak_gb_s": 448, "scope": "per BR100 OAM chip in an eight-card all-to-all topology", "state": "official" }, "package": { "description": "Two 537 mm² compute chiplets and four HBM2E stacks on TSMC CoWoS 2.5D", "state": "official" }, "software": [ "BIRENSUPA", "compiler", "runtime", "drivers", "libraries", "framework support" ], "availability": { "state": "reported", "status": "Silicon and systems demonstrated; Q4 2022 sampling announced. Continuing volume status is unclear following the reported TSMC suspension and related trade restrictions." }, "independent_validation": "Independent architectural analysis exists; neutral current silicon benchmarks and shipment volumes remain missing.", "sources": [ { "label": "Biren Hot Chips presentation", "url": "https://hc34.hotchips.org/assets/program/conference/day1/GPU%20HPC/HC2022.BirenTech.MikeHong.LingjieXu.v01.pdf", "state": "official" }, { "label": "Independent microarchitecture analysis", "url": "https://old.chipsandcheese.com/2022/10/04/hot-chips-34-birens-br100-a-machine-learning-gpu-from-china/", "state": "independent" } ], "unknowns": [ "current production volume", "BR104 memory and package", "post-control link rate", "independent silicon benchmarks" ], "entity_level": "datacenter_accelerator_family", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "GPU / GPGPU", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "metax-c500-c550", "company": "MetaX", "product": "C500 / C550", "role": "General-purpose GPGPU for training, inference, HPC, and graphics", "architecture": "XCORE GPGPU; C500 PCIe and C550 OAM", "process": { "node_nm": 7, "node_class": "advanced-constrained", "state": "reported", "note": "Broadly reported; current official page does not name the foundry or node." }, "compute": [ { "value": 30, "unit": "TFLOPS", "precision": "FP32", "scope": "reported/observed class; authoritative table unavailable", "state": "reported" } ], "memory": { "strategy": "hbm-reported", "hbm_free": false, "type": "HBM2E reported by server vendors", "capacity_gb": 64, "peak_bandwidth_tb_s": null, "bandwidth_scope": "capacity observed with mx-smi; bandwidth unknown", "state": "independent" }, "interconnect": { "peak_gb_s": null, "scope": "C500 PCIe 4.0; C550 OAM/PCIe 5.0 reported; optical and 3D-mesh systems exist but numeric link bandwidth is unknown", "state": "reported" }, "package": { "description": "Unknown", "state": "unknown" }, "software": [ "MXMACA", "MACA", "mxcc", "cucc", "operator libraries", "PyTorch" ], "availability": { "state": "official", "status": "C500 mass production and shipment since December 2023 according to MetaX; C550 is reported in deployed service" }, "independent_validation": "A public developer report shows an eight-C500 system, 64 GB per card, and a 350 W cap; a tested async-copy path underperformed its synchronous path, showing that source compatibility is not equal execution behavior.", "sources": [ { "label": "MetaX milestones", "url": "https://www.metax-tech.com/en/about/about.html", "state": "official" }, { "label": "Observed C500 developer system", "url": "https://developer.metax-tech.com/forum/t/ru-he-shi-yong-yi-bu-kao-bei-yi-da-dao-you-hua-de-xiao-guo-ni/215/", "state": "independent" } ], "unknowns": [ "primary memory type and bandwidth", "verified node", "package", "tensor rates", "link bandwidth", "independent application benchmarks" ], "entity_level": "datacenter_accelerator_family", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "GPU / GPGPU", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "metax-c600", "company": "MetaX", "product": "C600", "role": "Next-generation China-designed GPGPU for training, inference, and HPC", "architecture": "XCORE-class GPGPU; public final architecture incomplete", "process": { "node_nm": null, "node_class": "unknown", "state": "official", "note": "Company attributes the advanced process to China; the exact node, foundry, and facility remain unverified." }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "unknown", "state": "unknown" } ], "memory": { "strategy": "hbm-unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "144 GB appears in reseller material but is not treated as established", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "OAM and PCIe 5.0 reported; topology and bandwidth unknown", "state": "reported" }, "package": { "description": "Unknown", "state": "unknown" }, "software": [ "MXMACA" ], "availability": { "state": "official", "status": "Taped out October 2024 and brought up July 2025 according to MetaX; product listed, but public volume-shipment evidence not found" }, "independent_validation": "None found.", "sources": [ { "label": "MetaX", "url": "https://www.metax-tech.com/en", "state": "official" }, { "label": "MetaX milestones", "url": "https://www.metax-tech.com/en/about/about.html", "state": "official" } ], "unknowns": [ "final silicon specifications", "qualification", "production date", "memory", "interconnect", "package", "measured performance" ], "entity_level": "datacenter_accelerator_family", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "GPU / GPGPU", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "enflame-t20-t21", "company": "Enflame", "product": "T20 / T21", "role": "Datacenter training and inference accelerators", "architecture": "VLIW-style GCU cores with tensor/vector units, sparsity execution, and GCU-LARE interconnect", "process": { "node_nm": 12, "node_class": "mature-node-class", "state": "independent" }, "compute": [ { "value": 134.4, "unit": "TFLOPS", "precision": "FP16/BF16/TF32", "scope": "T20 company-era peak; sparsity convention requires confirmation", "state": "reported" }, { "value": 268.8, "unit": "TOPS", "precision": "INT8", "scope": "T20 company-era peak", "state": "reported" } ], "memory": { "strategy": "hbm", "hbm_free": false, "type": "HBM2E", "capacity_gb": 32, "peak_bandwidth_tb_s": null, "bandwidth_scope": "public figures conflict between about 0.819 and 1.6 TB/s", "state": "unknown" }, "interconnect": { "peak_gb_s": 300, "scope": "company-claimed GCU-LARE; direction and payload scope require confirmation", "state": "official" }, "package": { "description": "PCIe/OAM products; HBM package details unknown", "state": "unknown" }, "software": [ "TopsRider", "TopsPlatform", "PyTorch", "TensorFlow", "ONNX" ], "availability": { "state": "reported", "status": "Commercial hardware used in clusters; no current teardown found" }, "independent_validation": "Hot Chips architecture material and independent architectural reviews exist; current neutral workload data remain limited.", "sources": [ { "label": "Enflame Hot Chips presentation", "url": "https://hc33.hotchips.org/assets/program/conference/day2/Enflame_Final%20Deck.pdf", "state": "official" }, { "label": "ServeTheHome analysis", "url": "https://www.servethehome.com/enflame-dtu-1-0-ai-compute-chip-at-hot-chips-33/", "state": "independent" } ], "unknowns": [ "authoritative memory bandwidth", "package", "T20 versus T21 mapping", "production volume", "third-party workload performance" ], "entity_level": "datacenter_accelerator_family", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "NPU / tensor ASIC", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "enflame-s60", "company": "Enflame", "product": "S60", "role": "Later-generation inference and training card", "architecture": "GCU accelerator with a public Candle backend", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "unknown", "state": "unknown" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": 48, "peak_bandwidth_tb_s": null, "bandwidth_scope": "capacity shown by company examples; type and bandwidth unknown", "state": "official" }, "interconnect": { "peak_gb_s": null, "scope": "unknown", "state": "unknown" }, "package": { "description": "Unknown", "state": "unknown" }, "software": [ "TopsPlatform", "Ubridge", "UHHI", "Candle-GCU" ], "availability": { "state": "official", "status": "Company repository demonstrates working S60 hardware; public production volume and qualification remain unknown" }, "independent_validation": "Company-generated LLM examples exist; independent reproduction was not found.", "sources": [ { "label": "Enflame Candle-GCU", "url": "https://github.com/EnflameTechnology/candle-gcu", "state": "official" } ], "unknowns": [ "process", "compute", "memory type and bandwidth", "interconnect", "package", "power", "independent reproduction" ], "entity_level": "datacenter_accelerator_family", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "NPU / tensor ASIC", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "moore-threads-s4000", "company": "Moore Threads", "product": "MTT S4000", "role": "Datacenter GPU for AI, HPC, graphics, and media", "architecture": "Third-generation MUSA GPU with 8,192 vector cores and 128 tensor cores", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": 25, "unit": "TFLOPS", "precision": "FP32", "scope": "official dense peak", "state": "official" }, { "value": 100, "unit": "TFLOPS", "precision": "FP16 tensor", "scope": "official peak", "state": "official" }, { "value": 200, "unit": "TOPS", "precision": "INT8", "scope": "official peak", "state": "official" } ], "memory": { "strategy": "hbm-not-evidenced", "hbm_free": null, "type": "undisclosed conventional graphics memory", "capacity_gb": 48, "peak_bandwidth_tb_s": 0.768, "bandwidth_scope": "official peak", "state": "official" }, "interconnect": { "peak_gb_s": 240, "scope": "MTLink I/O/interface bandwidth; aggregate/directional scope and topology unclear", "state": "official" }, "package": { "description": "PCIe dual-slot board; no public HBM packaging evidence", "state": "official" }, "software": [ "MUSA", "MUSIFY", "driver", "runtime", "math libraries", "operator libraries", "communication libraries" ], "availability": { "state": "official", "status": "Shipping product with public manuals and kernel-development work" }, "independent_validation": "No neutral full-system benchmark or teardown found.", "sources": [ { "label": "Moore Threads product page", "url": "https://en.mthreads.com/product/S4000", "state": "official" }, { "label": "Official specification", "url": "https://docs.mthreads.com/s4000/s4000-doc-online/product_specifications/", "state": "official" }, { "label": "Official GEMM engineering work", "url": "https://blog.mthreads.com/blog/GEMM/2026-04-14-GEMM01/", "state": "official" } ], "unknowns": [ "process node", "memory type", "package detail", "exact MTLink topology", "sustained application efficiency", "neutral benchmarks" ], "entity_level": "datacenter_accelerator_card", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "GPU / GPGPU", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "iluvatar-bi-v150", "company": "Iluvatar CoreX", "product": "Tiangai 150 / BI-V150", "role": "Datacenter GPGPU for training, inference, and HPC", "architecture": "Second-generation general-purpose GPU", "process": { "node_nm": 7, "node_class": "advanced-constrained", "state": "reported" }, "compute": [ { "value": 48, "unit": "TFLOPS", "precision": "FP32", "scope": "reported peak", "state": "reported" }, { "value": 192, "unit": "TFLOPS", "precision": "FP16/BF16", "scope": "reported peak", "state": "reported" } ], "memory": { "strategy": "hbm", "hbm_free": false, "type": "HBM2E", "capacity_gb": 64, "peak_bandwidth_tb_s": null, "bandwidth_scope": "public figures conflict materially; left unknown", "state": "unknown" }, "interconnect": { "peak_gb_s": 64, "scope": "manual-copy shared bidirectional value; other reported values conflict", "state": "reported" }, "package": { "description": "2.5D CoWoS stated in a public manual copy", "state": "reported" }, "software": [ "IXUCA", "CoreX SDK", "framework compatibility", "virtualization", "vGPU" ], "availability": { "state": "independent", "status": "Commercial card supported by current HAMi device sharing and heterogeneous-cluster work" }, "independent_validation": "No teardown or credible neutral accelerator benchmark found.", "sources": [ { "label": "HAMi device support", "url": "https://project-hami.io/docs/next/userguide/iluvatar-device/enable-iluvatar-gpu-sharing", "state": "independent" } ], "unknowns": [ "reliable memory bandwidth", "foundry and node verification", "package teardown", "production volume", "neutral benchmark" ], "entity_level": "datacenter_accelerator_card", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "GPU / GPGPU", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "kunlunxin-p800", "company": "Kunlunxin / Baidu", "product": "P800", "role": "Datacenter training and inference XPU", "architecture": "Third-generation XPU-P optimized for MoE, MLA, and 8-bit inference", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown", "note": "Public reports conflict between 5 nm and 7 nm." }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "public figures conflict; no authoritative datasheet found", "state": "unknown" } ], "memory": { "strategy": "hbm-reported", "hbm_free": false, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "HBM2E/64 GB is widely reported but not established by the primary pages used", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "Eight-card systems and large clusters operate; numeric chip-link data remain unverified", "state": "unknown" }, "package": { "description": "Unknown", "state": "unknown" }, "software": [ "XPU stack", "PaddlePaddle", "PyTorch build", "KLX3 Triton", "vllm-kunlun", "xtorch_ops" ], "availability": { "state": "independent", "status": "Eight-card system passed a named CAICT DeepSeek adaptation test; large deployments are company-reported" }, "independent_validation": "CAICT adaptation artifact and a TechInsights floorplan analysis exist; accessible detailed silicon measurements remain incomplete.", "sources": [ { "label": "Kunlunxin qualification and deployment", "url": "https://www.kunlunxin.com/news/4471.html", "state": "official" }, { "label": "Kunlunxin architecture statement", "url": "https://www.kunlunxin.com/news/4720.html", "state": "official" }, { "label": "TechInsights floorplan analysis", "url": "https://www.techinsights.com/blog/baidu-kunlunxin-p800-ai-accelerator-processor-floorplan-analysis", "state": "independent" } ], "unknowns": [ "authoritative compute table", "process", "memory", "interconnect", "package", "power", "accessible teardown details" ], "entity_level": "datacenter_accelerator_family", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "NPU / tensor ASIC", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "horizon-journey-6", "company": "Horizon Robotics", "product": "Journey 6 family", "role": "Automotive ADAS and NOA SoC", "architecture": "BPU Nash with integrated CPU, GPU, MCU, ISP, and safety islands", "process": { "node_nm": 7, "node_class": "advanced-constrained", "state": "reported" }, "compute": [ { "value": 560, "unit": "effective TOPS", "precision": "family maximum", "scope": "official with one-half sparsity and TPP under 4,800; not dense datacenter BF16", "state": "official" } ], "memory": { "strategy": "lpddr", "hbm_free": true, "type": "LPDDR5X", "capacity_gb": null, "peak_bandwidth_tb_s": 0.204, "bandwidth_scope": "reported J6P 192-bit LPDDR5X-8533; capacity chosen by module/OEM", "state": "reported" }, "interconnect": { "peak_gb_s": null, "scope": "No datacenter-style accelerator scale-up link disclosed", "state": "unknown" }, "package": { "description": "Integrated automotive SoC/module; no HBM", "state": "official" }, "software": [ "OpenExplorer", "horizon_tc_ui", "HMCT", "HBDK4", "runtime", "model zoo" ], "availability": { "state": "official", "status": "Family launched in 2024; Journey 6 products are in vehicle production programs" }, "independent_validation": "A commercial J6E module teardown exists, but detailed results are paywalled. Production vehicle evidence exists.", "sources": [ { "label": "Horizon Journey 6", "url": "https://en.horizon.auto/solutions/horizon-journey", "state": "official" }, { "label": "Horizon toolchain guide", "url": "https://developer.horizon.auto/blog/13119", "state": "official" }, { "label": "J6E module teardown listing", "url": "https://www.reverse-costing.com/teardowns/horizon-robotics-journey-6-j6e-soc-module/", "state": "independent" } ], "unknowns": [ "variant memory capacity", "package and power by variant", "dense versus sparse rates", "public teardown measurements" ], "entity_level": "automotive_ai_soc_family", "entity_level_evidence_state": "derived", "entity_level_was_inferred": true, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type": "Integrated automotive AI accelerator", "accelerator_type_state": "derived", "accelerator_type_was_inferred": true, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_state": "derived", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "alibaba-t-head-hanguang-800", "candidate_id": "candidate-cn-alibaba-t-head-hanguang", "company": "Alibaba / T-Head", "product": "Hanguang 800", "entity_level": "internal_cloud_accelerator", "accelerator_type": "NPU / tensor ASIC", "role": "Machine-learning inference accelerator used inside Alibaba services", "architecture": "T-Head neural processing unit for search, translation, recommendation, advertising, and customer-service inference", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "No normalized like-for-like compute rate in the reviewed primary record", "state": "unknown" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "Memory technology, capacity, topology, and bandwidth are not stated in the reviewed primary sources", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "Unknown", "state": "unknown" }, "package": { "description": "Package and deployable hardware boundary not stated", "state": "unknown" }, "software": [ "HGAI model conversion and compilation path", "integration path for mainstream deep-learning inference frameworks" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Alibaba said on September 25, 2019 that Hanguang 800 was used internally, and later said it was deployed in Alibaba Cloud data centers; current merchant availability and deployment scale are not established" }, "independent_validation": "No independent product teardown, workload reproduction, current shipment receipt, or production-volume record is normalized here.", "sources": [ { "label": "Alibaba announcement of Hanguang 800", "url": "https://www.alibabagroup.com/en-US/document-1491206538574954496", "state": "official" }, { "label": "T-Head Hanguang NPU product page", "url": "https://www.t-head.cn/product/npu", "state": "official" }, { "label": "Alibaba account of Hanguang deployment", "url": "https://www.alibabagroup.com/en-US/document-1491124270925873152", "state": "official" } ], "unknowns": [ "process node and foundry", "memory type, capacity, and bandwidth", "package and system topology", "power", "external shipments", "current deployment scale", "customer qualification", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "tencent-zixiao-c100", "candidate_id": "candidate-cn-tencent-zixiao", "company": "Tencent", "product": "Zixiao C100", "entity_level": "cloud_accelerator_card", "accelerator_type": "NPU / tensor ASIC", "role": "Tencent Cloud AI inference accelerator used in PTX1 instances", "architecture": "Tencent Zixiao accelerator for computer vision, optical character recognition, natural-language processing, image, text, and speech inference", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": 120, "unit": "TFLOPS", "precision": "FP16", "scope": "Tencent Cloud PTX1 instance specification for one Zixiao C100 device; sustained application performance is not stated", "state": "official" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": 16, "peak_bandwidth_tb_s": null, "bandwidth_scope": "Tencent lists 16 GB of device memory; memory technology, placement, supplier, and bandwidth are not stated", "state": "official" }, "interconnect": { "peak_gb_s": null, "scope": "Unknown", "state": "unknown" }, "package": { "description": "C100 accelerator card inside Tencent Cloud PTX1 instances; die and package construction unknown", "state": "official" }, "software": [ "Tencent Cloud AI inference environment" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Tencent Cloud records PTX1 as launched in December 2022; this proves a named cloud-instance offering, not standalone card shipments or current volume" }, "independent_validation": "No independent chip benchmark, teardown, customer qualification record, or shipment-volume receipt is normalized here.", "sources": [ { "label": "Tencent sustainability report describing Zixiao", "url": "https://static.www.tencent.com/attachments/ssv/2021/TencentSSVReport2021.pdf", "state": "official" }, { "label": "Tencent Cloud PTX1 instance overview", "url": "https://cloud.tencent.com/document/product/560/19700", "state": "official" }, { "label": "Tencent Cloud PTX1 Zixiao C100 specifications", "url": "https://cloud.tencent.com/document/product/560/63395", "state": "official" } ], "unknowns": [ "process node and foundry", "memory technology and bandwidth", "die and package", "card power", "interconnect topology", "standalone card sales", "current cloud capacity", "customer qualification", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "hygon-dcu-8000", "candidate_id": "candidate-cn-hygon-dcu", "company": "Hygon", "product": "DCU 8000 series", "entity_level": "accelerator_family", "accelerator_type": "GPU / GPGPU", "role": "Data-center accelerator for scientific computing, AI training, inference, and large-model workloads", "architecture": "Hygon describes DCU as a GPGPU using a general parallel-computing architecture", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": "double, single, half precision, and integer formats supported", "scope": "The reviewed filing states supported format classes but does not provide a normalized generation-specific peak rate", "state": "official" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "Generation-specific memory technology, capacity, and bandwidth are not stated in the reviewed filings", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "Unknown", "state": "unknown" }, "package": { "description": "Server-cluster or data-center accelerator boundary stated; card and package construction unknown", "state": "unknown" }, "software": [ "DTK software stack", "self-developed operators", "third-party components" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Hygon filings say Deep Computing No. 1 completed product validation and entered commercial application in 2021, and had begun scaled sales by June 2022; the current 8000-series generation, volumes, and customer scope remain unnormalized" }, "independent_validation": "Exchange filings establish company statements and historical commercialization wording. They do not establish independent workload results, named customers, current shipment counts, or production yield.", "sources": [ { "label": "Hygon 2025 half-year report", "url": "https://star.sse.com.cn/disclosure/listedinfo/announcement/c/new/2025-08-06/688041_20250806_XTRO.pdf", "state": "official" }, { "label": "Hygon 2024 annual report", "url": "https://star.sse.com.cn/disclosure/listedinfo/announcement/c/new/2025-03-01/688041_20250301_608W.pdf", "state": "official" }, { "label": "Hygon March 2022 exchange response", "url": "https://static.sse.com.cn/stock/disclosure/announcement/c/202203/001043_20220304_7DDI.pdf", "state": "official" }, { "label": "Hygon June 2022 exchange response", "url": "https://static.sse.com.cn/stock/disclosure/announcement/c/202206/001043_20220622_HU33.pdf", "state": "official" } ], "unknowns": [ "current generation mapping", "process node and foundry", "memory type, capacity, and bandwidth", "package and interconnect", "power", "named customers", "current shipment volume", "qualification and yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "sophgo-bm1690", "candidate_id": "candidate-cn-sophgo-bitmain-ai-accelerators", "company": "SOPHGO", "product": "BM1690", "entity_level": "processor_family", "accelerator_type": "NPU / tensor ASIC", "role": "Integrated large-model training and inference processor", "architecture": "SOPHGO tensor processor supported through SOPHONSDK and TPU-MLIR tooling", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "No normalized BM1690 peak rate in the reviewed primary pages", "state": "unknown" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "Unknown", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "Unknown", "state": "unknown" }, "package": { "description": "Processor and system form factors not normalized for BM1690", "state": "unknown" }, "software": [ "SOPHONSDK", "TPU-MLIR", "multi-core MatMul support", "model regression tests", "operator-development path" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "SOPHGO records BM1690 as released in 2024 and documents continuing software enablement; the public record normalized here does not establish volume production or customer qualification" }, "independent_validation": "Software changelogs establish tool activity and regression testing, not production scale, customer acceptance, or independent workload performance.", "sources": [ { "label": "SOPHGO company and product history", "url": "https://www.sophgo.com/about-us/index.html", "state": "official" }, { "label": "SOPHGO English company and product history", "url": "https://en.sophgo.com/about-us/index.html", "state": "official" }, { "label": "SOPHGO BM1688 and CV186 SDK documentation", "url": "https://doc.sophgo.com/bm1688_sdk-docs/v1.7/docs_latest_release/docs/BM1688_CV186AH_SophonSDK_doc/0_introduction.html", "state": "official" }, { "label": "SOPHGO TPU-MLIR documentation", "url": "https://doc.sophgo.com/bm1688_sdk-docs/v2.1/docs_latest_release/docs/tpu-mlir/quick_start_en/index.html", "state": "official" } ], "unknowns": [ "process node and foundry", "memory technology and bandwidth", "package and interconnect", "power", "working-system scope", "volume production", "customer qualification", "shipments", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "denglin-goldwasser-l", "candidate_id": "candidate-cn-denglinai-gpgpu", "company": "DenglinAI", "product": "Goldwasser I L series", "entity_level": "accelerator_card_family", "accelerator_type": "GPU / GPGPU", "role": "Low-power enterprise and edge inference accelerator family", "architecture": "Denglin GPU+ accelerator supported by the Hamming software stack", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "No normalized like-for-like peak rate in the reviewed primary product pages", "state": "unknown" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": 64, "capacity_scope": "L128/L256 family lists 16 GB, 32 GB, and 64 GB configurations; 64 GB is the family maximum, not every card", "peak_bandwidth_tb_s": 0.239, "bandwidth_scope": "Company peak for L128/L256; memory technology and sustained bandwidth are not stated", "state": "official" }, "interconnect": { "peak_gb_s": null, "scope": "Unknown", "state": "unknown" }, "package": { "description": "Enterprise accelerator-card family; die and package construction unknown", "state": "official" }, "power": { "value": 25, "unit": "W", "scope": "Company typical-power specification for the L128/L256 product table", "state": "official" }, "software": [ "Hamming software stack", "mainstream AI-model inference path" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Denglin currently lists Goldwasser I L, Goldwasser II GS, and third-generation KS lines; current shipment quantity, customer qualification, and readiness of later generations are not established" }, "independent_validation": "No independent product benchmark, teardown, production-volume record, or named customer acceptance receipt is normalized here.", "sources": [ { "label": "DenglinAI corporate and product site", "url": "https://denglinai.com/", "state": "official" }, { "label": "DenglinAI Goldwasser L-series page", "url": "https://denglinai.com/h-col-251.html", "state": "official" }, { "label": "DenglinAI product hierarchy", "url": "https://denglinai.com/h-col-301.html", "state": "official" }, { "label": "Shanghai government record on historical Denglin BI chip", "url": "https://www.sheitc.sh.gov.cn/gydt/20210618/a1c454e86b944440a5c4bca06f2bb0b4.html", "state": "official" } ], "unknowns": [ "Goldwasser process node and foundry", "memory technology", "sustained bandwidth", "package construction", "interconnect", "later-generation specifications", "shipment volume", "customer qualification", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "vastai-va10-family", "candidate_id": "candidate-cn-vastai-ai-accelerators", "company": "Vastai Technologies", "product": "VA10 family", "entity_level": "accelerator_and_system_family", "accelerator_type": "GPU / GPGPU", "role": "Data-center inference GPU family for large-language-model and media workloads", "architecture": "Vastai Unified Compute Architecture full-function GPU family spanning accelerator cards and appliances", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "No normalized like-for-like card compute rate in the reviewed primary pages", "state": "unknown" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "Vastai states up to 2 TB of whole-appliance memory for VA10L/VGX VA16 systems; card memory type, card capacity, and bandwidth are not established", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "System interconnect topology and rate are not normalized", "state": "unknown" }, "package": { "description": "VA10-family accelerator cards and VGX VA16 appliance boundary; die and package construction unknown", "state": "official" }, "software": [ "VUCA", "Kylin", "UnionTech OS", "Anolis OS", "openEuler", "company-stated model adaptation for Llama, Qwen, Baichuan, ChatGLM, and Stable Diffusion" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Vastai says two chip generations reached mass production and commercialization, and called VA1L and VA10L mass-produced in September 2024; audited units, named recipients, current availability, and qualification remain unknown" }, "independent_validation": "Company mass-production and model-adaptation wording is not independent testing and does not establish shipment volume or workload parity.", "sources": [ { "label": "Vastai company history and readiness claims", "url": "https://www.vastaitech.com/company/about", "state": "official" }, { "label": "Vastai product overview", "url": "https://www.vastaitech.com/", "state": "official" }, { "label": "Vastai VA10L appliance announcement", "url": "https://www.vastaitech.com/newsroom/company-news/55", "state": "official" }, { "label": "Vastai VGX VA16 announcement", "url": "https://www.vastaitech.com/newsroom/company-news/56", "state": "official" } ], "unknowns": [ "process node and foundry", "card memory type, capacity, and bandwidth", "package and interconnect", "card power", "named customers", "audited shipment volume", "qualification and yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "axera-ax650-family", "candidate_id": "candidate-cn-axera-edge-automotive-ai-socs", "company": "Axera", "product": "AX650 family", "entity_level": "edge_ai_soc_family", "accelerator_type": "Integrated client or edge AI accelerator", "role": "Edge AI inference and vision system-on-chip family", "architecture": "Axera Neutron NPU integrated with Arm CPU, AI image-signal processing, and video engines", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": 10.8, "unit": "TOPS", "precision": "INT8", "scope": "AX650N vendor peak; the same source states 43.2 TOPS at INT4", "state": "official" }, { "value": 43.2, "unit": "TOPS", "precision": "INT4", "scope": "AX650N vendor peak; not comparable with INT8, FP16, or application throughput without a matched workload", "state": "official" } ], "memory": { "strategy": "lpddr", "hbm_free": true, "type": "64-bit LPDDR4X interface", "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "AX650N interface support; device capacity, memory supplier, and sustained bandwidth are not stated", "state": "official" }, "interconnect": { "peak_gb_s": null, "scope": "Peripheral interfaces are documented, but no data-center scale-up fabric applies to this SoC record", "state": "unknown" }, "package": { "description": "Integrated edge AI SoC; separate 1050-series DIMM system-on-module products use AX650-family silicon", "state": "official" }, "software": [ "Axera SDK", "AX-LLM evaluation repository", "mainstream deep-learning framework conversion path" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Axera's 2026 prospectus defines AX650 as a commercialized endpoint-computing series; this means external-sale revenue was recognized, not that current volume, customers, or profitability are established" }, "independent_validation": "PSA Certified Level 1 is a bounded security-certification receipt for named products. It does not establish automotive functional safety, workload performance, volume, or complete-system qualification.", "sources": [ { "label": "Axera 2026 prospectus", "url": "https://www.axera-tech.com/sites/default/files/2026-01/2026013000010_c.pdf", "state": "official" }, { "label": "Axera AX650N product announcement", "url": "https://axera-tech.com/en/news/2819.html", "state": "official" }, { "label": "Axera 1050-series system-on-module page", "url": "https://www.axera-tech.com/en/node/2992", "state": "official" }, { "label": "Axera PSA Certified Level 1 announcement", "url": "https://axera-tech.com/en/news/2779.html", "state": "official" }, { "label": "Axera AX-LLM repository", "url": "https://github.com/AXERA-TECH/ax-llm", "state": "official" } ], "unknowns": [ "process node and foundry", "device memory capacity and supplier", "sustained bandwidth", "package and test provider", "power for the normalized device boundary", "named customers", "current volume and yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "intellifusion-deepedge10-family", "candidate_id": "candidate-cn-intellifusion-ai-accelerators", "company": "Intellifusion", "product": "DeepEdge10 family", "entity_level": "edge_ai_soc_family", "accelerator_type": "Integrated client or edge AI accelerator", "role": "Edge video, machine-vision, robotics, industrial-control, and private edge-model inference SoC family", "architecture": "DeepEdge10C, DeepEdge10, and DeepEdge10Max use Intellifusion's NNP400T neural processor; DeepEdge10Max adds a vendor-described D2D chiplet interconnect for scalable edge inference", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": 8, "unit": "TOPS", "precision": "INT8", "scope": "DeepEdge10C vendor peak; the same page lists 4 TOPS INT16 and 1.5 TFLOPS FP16", "state": "official" }, { "value": 16, "unit": "TOPS", "precision": "INT8", "scope": "DeepEdge10 vendor peak; the same page lists 8 TOPS INT16 and 2 TFLOPS FP16", "state": "official" }, { "value": 64, "unit": "TOPS", "precision": "INT8", "scope": "DeepEdge10Max vendor peak; the same page lists 32 TOPS INT16 and 8 TFLOPS FP16", "state": "official" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "The official page lists 4 GB LPDDR4X on an IPU X200 module using DeepEdge10C and 8 GB LPDDR4X on an IPU A300 module using DeepEdge10; it does not establish a family-wide chip memory interface, topology, supplier, or bandwidth", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "DeepEdge10Max uses a vendor-described D2D chiplet interconnect; topology, die count, protocol, and rate are not stated", "state": "official" }, "package": { "description": "Integrated edge SoC family; DeepEdge10Max is described as a chiplet design, but die and package construction are not disclosed", "state": "official" }, "software": [ "model quantization, compilation, and deployment SDK", "PyTorch", "ONNX", "TensorFlow", "support for CNN, RNN, Transformer, and GNN networks" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Intellifusion currently lists DeepEdge10C, DeepEdge10, and DeepEdge10Max as chip products and lists modules and cards built around its processors; this does not establish shipment volume, named recipients, or current production capacity" }, "independent_validation": "No independent teardown, matched-workload benchmark, customer qualification, shipment count, or production-yield receipt is normalized here.", "sources": [ { "label": "Intellifusion AI chip and module catalog", "url": "https://www.intellif.com/int/chips.html", "state": "official" } ], "unknowns": [ "process node and foundry", "chip memory interface, capacity, supplier, and bandwidth", "D2D topology and bandwidth", "die and package construction", "chip and module power for the normalized family", "named customer qualification", "current shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "corerain-caisa-430", "candidate_id": "candidate-cn-corerain-dataflow", "company": "Corerain", "product": "CAISA 430", "entity_level": "edge_ai_accelerator_soc", "accelerator_type": "Dataflow or spatial ASIC", "role": "Reconfigurable dataflow chip for edge and higher-performance AI inference", "architecture": "Fourth-generation CAISA 4.0 reconfigurable dataflow architecture with a 24-core Arm Cortex-A55 CPU complex and support for CNN, RNN, and Transformer networks", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": 16, "unit": "TOPS", "precision": "INT8", "scope": "Vendor peak for CAISA 430; the same page says INT16 and FP32 are supported without normalized peak rates", "state": "official" } ], "memory": { "strategy": "lpddr", "hbm_free": true, "type": "LPDDR4X", "capacity_gb": 48, "capacity_scope": "Vendor maximum across three LPDDR4X channels, not a statement that every implementation carries 48 GB", "peak_bandwidth_tb_s": 0.0896, "bandwidth_scope": "Vendor peak of 89.6 GB/s for the stated three-channel LPDDR4X memory path; sustained application bandwidth is not stated", "state": "official" }, "interconnect": { "peak_gb_s": null, "scope": "External scale-up, scale-out, and chip-to-chip interconnect are not stated", "state": "unknown" }, "package": { "description": "Integrated accelerator SoC; die size, package type, assembly, and test path are not stated", "state": "unknown" }, "software": [ "RainBuilder compiler toolchain", "TensorFlow", "PyTorch", "Caffe", "ONNX", "MXNet" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Corerain currently lists CAISA 430 as an orderable-inquiry product and shows systems based on the architecture; the page does not establish shipment volume, current production capacity, or customer qualification" }, "independent_validation": "Vendor utilization and peak-throughput statements are not independent workload measurements and do not establish sustained model performance, power efficiency, or volume production.", "sources": [ { "label": "Corerain CAISA 4.0 architecture and RainBuilder page", "url": "https://www.corerain.com/caisa.html", "state": "official" }, { "label": "Corerain CAISA 430 product specifications", "url": "https://www.corerain.com/products/caisa430.html", "state": "official" } ], "unknowns": [ "process node and foundry", "memory supplier and sustained bandwidth", "die and package construction", "external interconnect", "power", "named customer qualification", "current shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "corerain-n460h", "candidate_id": "candidate-cn-corerain-dataflow", "company": "Corerain", "product": "Stellar N460H", "entity_level": "accelerator_card", "accelerator_type": "Dataflow or spatial ASIC", "role": "Half-height, half-length inference card for x86 and Arm servers, small hosts, and industrial computers", "architecture": "Corerain high-performance AI inference card with a vendor-listed three-by-24-core Arm Cortex-A55 controller configuration; accelerator die count and package topology are not stated", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": 48, "unit": "TOPS", "precision": "INT8", "scope": "N460H vendor peak; not sustained application throughput", "state": "official" }, { "value": 12, "unit": "TOPS", "precision": "INT16", "scope": "N460H vendor peak; not directly comparable with INT8 or FP32 rates", "state": "official" }, { "value": 384, "unit": "GFLOPS", "precision": "FP32", "scope": "N460H vendor peak; sustained workload performance is not stated", "state": "official" } ], "memory": { "strategy": "lpddr", "hbm_free": true, "type": "LPDDR4X", "capacity_gb": 144, "capacity_scope": "Vendor maximum; the standard N460H configuration is listed as 72 GB", "peak_bandwidth_tb_s": null, "bandwidth_scope": "Memory bandwidth, topology, and supplier are not stated on the N460H card page", "state": "official" }, "interconnect": { "peak_gb_s": null, "scope": "Vendor lists a PCIe Gen3 x8 physical interface and a PCIe Gen3 x2 data-link interface; measured host-transfer throughput and multi-card fabric are not stated", "state": "official" }, "package": { "description": "Passive, single-slot, half-height half-length card measuring 169.5 by 69.2 by 18.5 mm; accelerator die and package construction are unknown", "state": "official" }, "power": { "value": 75, "unit": "W", "scope": "Vendor maximum card power, stated as no more than 75 W", "state": "official" }, "software": [ "OpenEuler operating system by default", "RainBuilder compiler toolchain" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Corerain currently lists N460H as a product with ordering inquiry; this establishes a vendor-offered card specification, not stock, shipment volume, named customer qualification, or installed capacity" }, "independent_validation": "No independent card teardown, measured host-transfer result, sustained model benchmark, qualification record, or shipment count is normalized here.", "sources": [ { "label": "Corerain CAISA 4.0 architecture and RainBuilder page", "url": "https://www.corerain.com/caisa.html", "state": "official" }, { "label": "Corerain Stellar N460H product specifications", "url": "https://www.corerain.com/products/N460H.html", "state": "official" } ], "unknowns": [ "accelerator die count and process node", "foundry, assembly, and test provider", "memory supplier and bandwidth", "package construction", "measured PCIe throughput and multi-card fabric", "named customer qualification", "current shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "tsingmicro-tx5-family", "candidate_id": "candidate-cn-tsingmicro-reconfigurable-ai", "company": "TsingMicro", "product": "TX5 family", "entity_level": "edge_ai_soc_family", "accelerator_type": "Integrated client or edge AI accelerator", "role": "Professional edge-vision, industrial-inspection, robotics, and edge-model inference SoC family", "architecture": "TX5 family uses TsingMicro's reconfigurable neural-network engine; individual members add CGRA image processing, general-compute acceleration, GPU or 3D engines, video codecs, and vision-processing blocks", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": "W4A8 mixed-precision quantization supported on TX5326", "scope": "The reviewed family page does not provide a normalized numeric peak for TX5326, TX5336, TX5368, or TX5215", "state": "official" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "The vendor says its architecture reduces DDR consumption but does not state memory type, capacity, topology, supplier, or bandwidth for the family", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "External interfaces and inter-chip links are not normalized on the reviewed family page", "state": "unknown" }, "package": { "description": "Integrated edge SoC family including TX5326, TX5336, TX5368, and TX5215; package construction is not stated", "state": "official" }, "software": [ "vendor-described mature deployment toolchain", "mainstream-framework compatibility", "intelligent quantization", "Transformer, LLM, and VLM edge-model support" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "TsingMicro says the TX5 family is in scaled mass production; this is a vendor readiness claim and does not establish audited units, named recipients, current capacity, or qualification" }, "independent_validation": "No independent teardown, framework reproduction, matched-workload result, qualification receipt, or audited shipment count is normalized here.", "sources": [ { "label": "TsingMicro TX5 professional edge-chip family", "url": "https://www.tsingmicro.com/products/tx5/security-grade", "state": "official" } ], "unknowns": [ "generation-specific peak compute", "process node and foundry", "memory type, capacity, supplier, and bandwidth", "external interconnect", "die and package construction", "generation-specific power", "named customer qualification", "audited shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "black-sesame-huashan-a1000-family", "candidate_id": "candidate-cn-black-sesame-huashan-wudang", "company": "Black Sesame Technologies", "product": "Huashan A1000 family", "entity_level": "automotive_ai_soc_family", "accelerator_type": "Automotive AI system-on-chip", "role": "Automotive driving-assistance SoC family for L2+ and L3 functions and related commercial-vehicle applications", "architecture": "Huashan automotive SoC family consisting of A1000, A1000L, and A1000 Pro; the reviewed filing describes proprietary IP cores and an integrated driving-compute platform without disclosing a normalized microarchitecture", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "The reviewed 2025 annual report does not provide generation-normalized peak compute rates for A1000, A1000L, and A1000 Pro", "state": "unknown" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "Memory technology, capacity, topology, supplier, and bandwidth are not stated in the reviewed filing", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "Vehicle, sensor, die-to-die, and external accelerator interconnect rates are not normalized in the reviewed filing", "state": "unknown" }, "package": { "description": "Automotive SoC family; die, package, assembly, and test construction are not stated", "state": "unknown" }, "software": [ "Hanhai ADAS middleware platform", "peripheral open interfaces and commonly used basic software components" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Black Sesame's 2025 annual report says the A1000 family achieved mass production and deployment, remained in vehicle programs, and was the main contributor to company chip sales in 2025; audited unit volume and product-level customer qualification are not stated" }, "independent_validation": "The exchange filing is a primary company record. Its product, certification, integration, and readiness wording is not an independent workload, safety, shipment-volume, or supply-chain validation.", "sources": [ { "label": "Black Sesame International 2025 annual report", "url": "https://www1.hkexnews.hk/listedco/listconews/sehk/2026/0427/2026042701016.pdf", "state": "official" } ], "unknowns": [ "generation-normalized compute", "process node and foundry", "memory type, capacity, supplier, and bandwidth", "package, assembly, and test path", "power", "product-level customer qualification", "audited shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "jingjia-micro-jm11-family", "candidate_id": "candidate-cn-jingjia-micro-graphics-compute", "company": "Jingjia Micro", "product": "JM11 family", "entity_level": "gpu_chip_family", "accelerator_type": "GPU / GPGPU", "role": "General desktop and cloud-rendering GPU family for cloud desktops, cloud gaming, rendering, workstation, GIS, multimedia, and industrial-design workloads", "architecture": "Jingjia Micro GPU family with hardware virtualization and passthrough virtualization support; the reviewed filing does not disclose a normalized microarchitecture", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "No normalized peak compute rate is stated for the JM11 family in the reviewed filing", "state": "unknown" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "Memory technology, capacity, topology, supplier, and bandwidth are not stated in the reviewed filing", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "Host and multi-GPU interconnect are not stated in the reviewed filing", "state": "unknown" }, "package": { "description": "GPU chip family used across servers, graphics workstations, desktops, and notebooks; card, module, die, and package boundaries are not normalized", "state": "unknown" }, "software": [ "Windows", "Linux", "mainstream operating systems used in China", "hardware virtualization", "passthrough virtualization" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Jingjia Micro's 2025 annual report lists JM11 as released in 2025 and at the small-batch delivery-and-use stage; it also describes a 32-session cloud-desktop deployment, but does not disclose recipient identity, product units, or current production capacity" }, "independent_validation": "Company-reported application and concurrency wording is not an independent benchmark, product teardown, customer acceptance record, or audited shipment count.", "sources": [ { "label": "Jingjia Micro 2025 annual report", "url": "https://static.cninfo.com.cn/finalpage/2026-04-24/1225166816.PDF", "state": "official" } ], "unknowns": [ "microarchitecture and generation-specific compute", "process node and foundry", "memory type, capacity, supplier, and bandwidth", "card, module, die, and package construction", "host and multi-GPU interconnect", "power", "named customer qualification", "audited shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "jingjia-micro-ch37-family", "candidate_id": "candidate-cn-jingjia-micro-graphics-compute", "company": "Jingjia Micro / Chengheng Micro", "product": "CH37 family", "entity_level": "edge_ai_soc_family", "accelerator_type": "Integrated client or edge AI accelerator", "role": "Integrated edge AI SoC family for robotics, AI boxes, intelligent terminals, recognition systems, and unmanned-aircraft payloads", "architecture": "Chengheng Micro high-integration single-chip SoC with CPU, GPU, NPU, GPGPU, ISP, DSP, and VPU processing blocks", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": 64, "unit": "TOPS", "precision": "INT8", "scope": "CH37 family vendor peak in Jingjia Micro's filing; sustained workload performance is not stated", "state": "official" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "Memory technology, capacity, topology, supplier, and bandwidth are not stated in the reviewed filing", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "Sensor, host, chip-to-chip, and network interfaces are not stated in the reviewed filing", "state": "unknown" }, "package": { "description": "High-integration single-chip edge AI SoC; die and package construction are not disclosed", "state": "official" }, "software": [ "supporting software under continued development according to the filing", "flexible compute-precision support" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Jingjia Micro's 2025 annual report places CH37 in the small-batch production stage and says customer introduction and software work are continuing; this does not establish audited units, named recipients, or qualification" }, "independent_validation": "The filing establishes the company's stated product and readiness stage, not an independent workload result, customer acceptance receipt, or audited production count.", "sources": [ { "label": "Jingjia Micro 2025 annual report", "url": "https://static.cninfo.com.cn/finalpage/2026-04-24/1225166816.PDF", "state": "official" } ], "unknowns": [ "generation variants and sustained workload performance", "process node and foundry", "memory type, capacity, supplier, and bandwidth", "external interfaces", "die and package construction", "numeric power", "named customer qualification", "audited shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "lisuan-lx-7g100", "candidate_id": "candidate-cn-lisuan-graphics", "company": "Lisuan Technology", "product": "LX 7G100", "entity_level": "discrete_graphics_card", "accelerator_type": "GPU / GPGPU", "role": "Consumer graphics card for gaming, local AI-PC applications, content creation, recording, streaming, and video processing", "architecture": "Lisuan TrueGPU graphics architecture with NRSS super-resolution support", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "The reviewed official product page does not provide a peak compute rate or a normalized AI-acceleration rate", "state": "unknown" } ], "memory": { "strategy": "gddr", "hbm_free": true, "type": "GDDR6", "capacity_gb": 12, "peak_bandwidth_tb_s": null, "bandwidth_scope": "The product page states 12 GB GDDR6; bus width, data rate, supplier, and bandwidth are not stated", "state": "official" }, "interconnect": { "peak_gb_s": null, "scope": "Host interface generation and measured transfer rate are not stated on the reviewed product page", "state": "unknown" }, "package": { "description": "294 by 120 by 49 mm discrete graphics card with active axial-fan cooling; GPU die and package construction are unknown", "state": "official" }, "software": [ "DirectX 12", "Vulkan 1.3", "OpenGL 4.6", "OpenCL 3.0", "Lisuan driver download center", "NRSS super resolution" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Lisuan currently lists LX 7G100 as a consumer product and links to online purchasing; this does not establish stock, shipments, sell-through, named customers, or production volume" }, "independent_validation": "No independent board teardown, driver-compatibility audit, matched gaming or AI benchmark, qualification receipt, or audited shipment count is normalized here.", "sources": [ { "label": "Lisuan LX 7G100 official product page", "url": "https://www.lisuantech.com/product/gaming-graphics/lx-7g100", "state": "official" } ], "unknowns": [ "GPU microarchitecture details and peak compute", "process node and foundry", "memory bus width, data rate, supplier, and bandwidth", "host interface", "GPU die and package construction", "board power", "named customer qualification", "audited shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "innosilicon-fenghua-3", "candidate_id": "candidate-cn-innosilicon-graphics-compute", "company": "Innosilicon", "product": "Fenghua 3", "entity_level": "accelerator_card_family", "accelerator_type": "GPU / GPGPU", "role": "Full-function GPU for large-model training and inference, scientific computing, graphics rendering, virtualization, and multi-display workloads", "architecture": "Full-function GPU with a vendor-described CUDA-compatible programming path and an integrated Nanhu V3 open-source RISC-V CPU", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": "single, double, and mixed precision supported", "scope": "The launch article describes supported precision classes and workloads but does not provide a normalized peak compute rate", "state": "official" } ], "memory": { "strategy": "high_bandwidth_discrete", "hbm_free": null, "type": "high-bandwidth video memory; technology not stated", "capacity_gb": 112, "capacity_scope": "Vendor says a single card carries 112 GB or more; 112 GB is a lower bound rather than a normalized exact SKU", "peak_bandwidth_tb_s": null, "bandwidth_scope": "The vendor calls the memory high bandwidth but does not state memory technology, supplier, interface width, data rate, or numeric bandwidth", "state": "official" }, "interconnect": { "peak_gb_s": null, "scope": "Host, card-to-card, and cluster interconnect are not stated in the reviewed launch article", "state": "unknown" }, "package": { "description": "Single-card product boundary is stated; physical form factor, die count, package construction, assembly, and test path are not disclosed", "state": "official" }, "software": [ "PyTorch", "Triton", "HIP and CUDA-compatible frameworks", "OpenCL", "DirectX 12", "Vulkan 1.2", "OpenGL 4.6", "UOS", "Kylin", "Windows", "Android", "vGPU virtualization" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Innosilicon says Fenghua 3 was launched on September 22, 2025, demonstrated at the event, and covered by ecosystem agreements for future systems and clusters; this does not establish working units outside the demonstration, current shipments, installed clusters, or production volume" }, "independent_validation": "Launch demonstrations and ecosystem agreements are vendor evidence, not an independent benchmark, teardown, customer acceptance record, shipment receipt, or production audit.", "sources": [ { "label": "Innosilicon Fenghua 3 launch article", "url": "https://www.innosilicon.cn/news/37", "state": "official" } ], "unknowns": [ "peak compute by precision", "process node and foundry", "memory technology, supplier, and numeric bandwidth", "host and scale-out interconnect", "physical card, die, and package construction", "power", "named customer qualification", "current shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "unisoc-t9100", "candidate_id": "candidate-cn-unisoc-client-edge-ai", "company": "UNISOC", "product": "T9100", "entity_level": "mobile_ai_soc", "accelerator_type": "Integrated client or edge AI accelerator", "role": "5G smartphone SoC with an integrated NPU for on-device AI, imaging, and security workloads", "architecture": "Octa-core Arm CPU with one Cortex-A76 at 2.7 GHz, three Cortex-A76 cores at 2.3 GHz, four Cortex-A55 cores at 2.1 GHz, an Arm Mali-G57 MC4 GPU, and an integrated NPU", "process": { "node_nm": 6, "node_class": "advanced", "state": "official" }, "compute": [ { "value": 8, "unit": "TOPS", "precision": null, "scope": "UNISOC peak NPU claim; precision, power envelope, utilization, and sustained application rate are not stated", "state": "official" } ], "memory": { "strategy": "lpddr", "hbm_free": true, "type": "LPDDR4X", "capacity_gb": 32, "capacity_scope": "UNISOC states support for up to 32 GB LPDDR4X at 2133 MHz; this is an interface maximum, not a device configuration or shipment claim", "peak_bandwidth_tb_s": null, "bandwidth_scope": "UNISOC states LPDDR4X at 2133 MHz and eMMC 5.1 or UFS 3.1 storage support; bus width and memory bandwidth are not stated", "state": "official" }, "interconnect": { "peak_gb_s": null, "scope": "No chip-to-chip or accelerator-fabric rate is stated on the reviewed product page", "state": "unknown" }, "package": { "description": "Mobile SoC; die, package, assembly, and test construction are not stated", "state": "unknown" }, "software": [ "access to mainstream AI training frameworks", "advanced model-compression tooling", "compatibility with more than 200 neural-network operators", "on-device AI development and debugging environment" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "UNISOC currently maintains a T9100 product page; the page does not establish a named device design win, customer qualification, shipment count, or current production volume" }, "independent_validation": "No independent teardown, device-level workload benchmark, named-customer qualification, shipment count, or production-yield receipt is normalized here.", "sources": [ { "label": "UNISOC T9100 product page", "url": "https://www.unisoc.com/en/product/SmartPhoneUS/T9100", "state": "official" } ], "unknowns": [ "process foundry and lithography route", "die size and transistor count", "package, assembly, and test path", "sustained NPU performance and power", "named device and customer qualification", "shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "unisoc-a7870", "candidate_id": "candidate-cn-unisoc-client-edge-ai", "company": "UNISOC", "product": "A7870 series", "entity_level": "automotive_cockpit_soc_family", "accelerator_type": "Integrated automotive AI accelerator", "role": "Automotive smart-cockpit, cockpit-and-parking, cockpit-and-driving, and integrated T-Box processing", "architecture": "Octa-core Arm CPU with one Cortex-A76 at 2.7 GHz, three Cortex-A76 cores at 2.3 GHz, four Cortex-A55 cores at 2.1 GHz, a four-core NATT GPU at 850 MHz, and an IMG AX3596 NPU", "process": { "node_nm": 6, "node_class": "advanced", "state": "official" }, "lithography": { "description": "UNISOC product page labels the process TSMC 6nm EUV", "path": "vendor product-page label", "state": "official", "scope": "not independent foundry, scanner, facility, volume, yield, or China-developed DUV/EUV capability proof" }, "compute": [ { "value": 8, "unit": "TOPS", "precision": null, "scope": "UNISOC peak IMG AX3596 NPU claim; precision, power envelope, utilization, and sustained application rate are not stated", "state": "official" }, { "value": 486.4, "unit": "GFLOPS", "precision": null, "scope": "UNISOC peak NATT GPU claim in the product overview; the parameter table rounds the same GPU claim to 486 GFLOPS", "state": "official" } ], "memory": { "strategy": "lpddr", "hbm_free": true, "type": "LPDDR4X", "capacity_gb": 32, "capacity_scope": "UNISOC states support for up to 32 GB LPDDR4X at 2133 MHz; this is an interface maximum, not a vehicle configuration", "peak_bandwidth_tb_s": null, "bandwidth_scope": "UNISOC states LPDDR4X at 2133 MHz and eMMC 5.1 or UFS 3.1 storage support; bus width and memory bandwidth are not stated", "state": "official" }, "interconnect": { "peak_gb_s": null, "scope": "UNISOC lists PCIe 3.0, MIPI DSI, DisplayPort 1.4, CSI, UFS 3.1, I2S, and other system interfaces; lane topology, chip-to-chip fabric, and sustained rate are not stated", "state": "official" }, "package": { "description": "Automotive cockpit SoC family; die, package, assembly, and test construction are not stated", "state": "unknown" }, "software": [ "QNX", "Linux", "Android Automotive", "virtual-machine multi-baseline cockpit software", "integrated cockpit, parking, and T-Box solution path" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "UNISOC lists the A7870 series as an automotive-grade smart-cockpit processor and uses AEC-Q100 process-system and support wording; the reviewed page does not establish a named vehicle, customer qualification, mass-production start, or shipment volume" }, "independent_validation": "The UNISOC product page labels the process as 'TSMC 6nm EUV.' This packet records that exact label only as an official UNISOC claim, not as independent foundry, lithography-tool, wafer-production, facility, volume, or yield proof. No independent teardown, vehicle benchmark, or qualification receipt is normalized here.", "sources": [ { "label": "UNISOC A7870 series product page", "url": "https://www.unisoc.com/cn/product/SmartCar/A7870", "state": "official" } ], "unknowns": [ "independent foundry confirmation of the vendor-stated TSMC 6nm EUV label", "lithography tools, wafer facility, and production route", "die size and transistor count", "package, assembly, and test path", "sustained NPU and GPU performance and power", "named vehicle and customer qualification", "shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "rockchip-rk3588", "candidate_id": "candidate-cn-rockchip-client-edge-npu", "company": "Rockchip", "product": "RK3588", "entity_level": "edge_compute_soc", "accelerator_type": "Integrated client or edge AI accelerator", "role": "Edge-compute, multimedia, and machine-vision SoC with an integrated NPU", "architecture": "Quad-core Arm Cortex-A76 plus quad-core Cortex-A55 CPU, Arm Mali-G610 MC4 GPU, and triple-core NPU", "process": { "node_nm": 8, "node_class": "advanced", "state": "official" }, "compute": [ { "value": 6, "unit": "TOPS", "precision": "INT4 / INT8 / INT16 / FP16 / BF16 / TF32 support", "scope": "Rockchip aggregate NPU peak claim; the page lists supported arithmetic formats but does not map 6 TOPS to a specific precision or sustained workload", "state": "official" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "Memory interface, type, capacity, supplier, topology, and bandwidth are not stated on the reviewed official product page", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "Rockchip lists PCIe 3.0, PCIe 2.0, SATA 3.0, RGMII, USB Type-C, USB 3.1, and USB 2.0; lane topology and sustained rates are not stated and these are not a normalized accelerator fabric", "state": "official" }, "package": { "description": "Edge-compute SoC; die, package, assembly, and test construction are not stated", "state": "unknown" }, "software": [ "Android", "Linux", "OpenCL 1.1, 1.2, and 2.0 GPU support" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Rockchip currently maintains an RK3588 product page; that page does not establish named board or device availability, customer qualification, shipment count, or current production volume" }, "independent_validation": "No independent teardown, matched-workload benchmark, board-level acceptance record, shipment count, or production-yield receipt is normalized here.", "sources": [ { "label": "Rockchip RK3588 product page", "url": "https://www.rock-chips.com/a/en/products/RK35_Series/2022/0926/1660.html", "state": "official" } ], "unknowns": [ "process foundry and lithography route", "memory type, capacity, supplier, and bandwidth", "package, assembly, and test path", "precision-specific peak and sustained NPU performance", "power", "named board, device, and customer qualification", "shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "allwinner-v853", "candidate_id": "candidate-cn-allwinner-client-edge-npu", "company": "Allwinner", "product": "V853", "entity_level": "edge_ai_vision_soc", "accelerator_type": "Integrated vision NPU", "role": "Low-power AI-vision SoC for smart cameras, access systems, dash cameras, and other embedded image-processing products", "architecture": "Arm Cortex-A7 CPU up to 1.2 GHz, RISC-V XuanTie E907 MCU up to 600 MHz, integrated NPU, Allwinner codec engine, and image-signal processor", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": 1, "unit": "TOPS", "precision": "INT8", "scope": "Allwinner peak NPU claim; power envelope, utilization, and sustained application rate are not stated", "state": "official" } ], "memory": { "strategy": "ddr", "hbm_free": true, "type": "DDR3 / DDR3L", "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "Allwinner lists DDR3 and DDR3L support plus SD 3.0, eMMC 5.0, SPI NOR, and SPI NAND storage; capacity, bus width, supplier, and bandwidth are not stated", "state": "official" }, "interconnect": { "peak_gb_s": null, "scope": "Allwinner lists USB, SMHC, GPIO, SPI, TWI, UART, GMAC, GPADC, PWM, and other peripheral interfaces; no accelerator-fabric rate is stated", "state": "official" }, "package": { "description": "Embedded vision SoC; die, package, assembly, and test construction are not stated", "state": "unknown" }, "software": [ "Tina Linux", "FreeRTOS" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Allwinner currently maintains a V853 product page and lists target applications; the examples are product positioning, not named design wins, customer qualification, shipment counts, or production-volume receipts" }, "independent_validation": "No independent teardown, device-level workload benchmark, named-customer qualification, shipment count, or production-yield receipt is normalized here.", "sources": [ { "label": "Allwinner V853 product page", "url": "https://www.allwinnertech.com/index.php?c=product&id=117", "state": "official" } ], "unknowns": [ "process node, foundry, and lithography route", "memory capacity, supplier, and bandwidth", "package, assembly, and test path", "sustained NPU performance and power", "named device and customer qualification", "shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "nio-shenji-nx9031", "candidate_id": "candidate-cn-nio-automotive-silicon", "company": "NIO", "product": "Shenji NX9031", "entity_level": "automotive_smart_driving_chip", "accelerator_type": "Automotive smart-driving accelerator", "role": "In-vehicle compute for assisted and intelligent-driving features", "architecture": "NIO describes Shenji NX9031 as its proprietary automotive-grade smart-driving chip; the reviewed primary source does not disclose a normalized CPU, GPU, NPU, or tensor architecture", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "No precision-specific peak or sustained compute rate is stated in the reviewed NIO release", "state": "unknown" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "Memory technology, capacity, topology, supplier, and bandwidth are not stated in the reviewed NIO release", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "Vehicle, sensor, die-to-die, and chip-to-chip interconnect topology and rates are not stated in the reviewed NIO release", "state": "unknown" }, "package": { "description": "Automotive smart-driving chip; die, package, assembly, and test construction are not stated", "state": "unknown" }, "software": [ "NIO assisted and intelligent-driving feature stack" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "NIO said ET9 deliveries began on March 29, 2025 and that two Shenji NX9031 chips were integrated into every ET9. This establishes vehicle integration at the stated launch, not delivered ET9 quantity, broader-model deployment, customer qualification, or chip production volume" }, "independent_validation": "The NIO release is a primary company receipt for the stated ET9 delivery start and two-chip configuration. It is not an independent teardown, workload, safety, field-reliability, unit-volume, supply-chain, or yield validation.", "sources": [ { "label": "NIO Auto Shanghai 2025 release", "url": "https://www.nio.com/news/20250423001", "state": "official" } ], "unknowns": [ "compute architecture, precision-specific performance, and power", "process node, foundry, and lithography route", "memory type, capacity, supplier, and bandwidth", "package, assembly, and test path", "independent customer qualification and safety validation", "delivered ET9 count using the chip", "chip shipment and production volume", "yield and field reliability", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "xpeng-turing-ai-chip", "candidate_id": "candidate-cn-xpeng-automotive-silicon", "company": "XPeng", "product": "XPENG Turing chip", "entity_level": "automotive_and_robotics_ai_chip_program", "accelerator_type": "Automotive, robotics, and eVOTL AI accelerator", "role": "Planned processing hardware for AI-defined vehicles, robots, and electric vertical-takeoff-and-landing aircraft", "architecture": "XPeng unveiled the Turing chip as part of its AI architecture and said it is applicable to robots, AI-defined cars, and eVOTLs; the reviewed product-specific release does not disclose a normalized accelerator architecture", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "No product-specific peak or sustained compute rate is stated in the reviewed XPeng release and filing", "state": "unknown" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "Memory technology, capacity, topology, supplier, and bandwidth are not stated in the reviewed product-specific source", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "Vehicle, sensor, die-to-die, and chip-to-chip interconnect topology and rates are not stated in the reviewed product-specific source", "state": "unknown" }, "package": { "description": "AI-chip program for vehicles, robots, and eVOTLs; die, package, assembly, and test construction are not disclosed", "state": "unknown" }, "software": [ "XPENG AI architecture" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "XPeng unveiled the Turing chip on August 27, 2024. The reviewed sources do not establish a product-specific vehicle integration, customer qualification, completed production ramp, shipment, or current merchant-availability receipt" }, "independent_validation": "XPeng's separate 2024 annual filing says unnamed processing hardware taped out in August 2024 and warns that development, design wins, and production ramp may not succeed. This packet does not convert that generic filing language into Turing-specific production proof. No independent teardown or workload receipt is normalized here.", "sources": [ { "label": "XPeng August 2024 delivery release and Turing unveiling", "url": "https://www.sec.gov/Archives/edgar/data/1810997/000119312524211475/d839068dex991.htm", "state": "official" }, { "label": "XPeng 2024 annual report processing-hardware risk disclosure", "url": "https://www.sec.gov/Archives/edgar/data/1810997/000119312525082001/d898600d20f.htm", "state": "official" } ], "unknowns": [ "product-specific tape-out linkage and silicon validation", "compute architecture, precision-specific performance, and power", "process node and identity of the unnamed foundry supplier", "memory type, capacity, supplier, and bandwidth", "package, assembly, and test suppliers", "vehicle, robot, or eVOTL integration and customer qualification", "shipment and production volume", "yield", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." }, { "id": "li-auto-mahe-m100", "candidate_id": "candidate-cn-li-auto-automotive-silicon", "company": "Li Auto", "product": "MAHE M100", "entity_level": "automotive_autonomous_driving_inference_chip", "accelerator_type": "Automotive autonomous-driving inference accelerator", "role": "In-vehicle inference hardware designed to operate with Li Auto's autonomous-driving algorithms", "architecture": "Li Auto describes M100 as its proprietary autonomous-driving inference chip designed for synergy with its full-stack autonomous-driving algorithms; the reviewed filings do not disclose a normalized CPU, GPU, NPU, or tensor architecture", "process": { "node_nm": null, "node_class": "unknown", "state": "unknown" }, "compute": [ { "value": null, "unit": null, "precision": null, "scope": "No precision-specific peak or sustained compute rate is stated in the reviewed Li Auto filings", "state": "unknown" } ], "memory": { "strategy": "unknown", "hbm_free": null, "type": null, "capacity_gb": null, "peak_bandwidth_tb_s": null, "bandwidth_scope": "Memory technology, capacity, topology, supplier, and bandwidth are not stated in the reviewed Li Auto filings", "state": "unknown" }, "interconnect": { "peak_gb_s": null, "scope": "Vehicle, sensor, die-to-die, and chip-to-chip interconnect topology and rates are not stated in the reviewed Li Auto filings", "state": "unknown" }, "package": { "description": "Automotive autonomous-driving inference chip; die, package, assembly, and test construction are not stated", "state": "unknown" }, "software": [ "Li Auto full-stack autonomous-driving algorithms", "MindVLA large model and 3D ViT Encoder in the all-new Li L9 vehicle configuration" ], "software_evidence_state": "official", "availability": { "state": "official", "status": "Li Auto said it launched and began deliveries of the all-new Li L9 in May 2026: the Ultra uses one proprietary MAHE M100 and the Livis uses two. This establishes the stated vehicle configuration and delivery start, not delivered-unit count, chip shipment volume, or independent vehicle qualification" }, "independent_validation": "Li Auto's SEC-filed results release is a primary company receipt for the stated May 2026 Li L9 launch, delivery start, and M100 configurations. It is not an independent teardown, matched driving-workload benchmark, safety, field-reliability, unit-volume, supply-chain, or yield validation.", "sources": [ { "label": "Li Auto 2025 annual report", "url": "https://www.sec.gov/Archives/edgar/data/1791706/000110465926041705/li-20251231x20f.htm", "state": "official" }, { "label": "Li Auto first-quarter 2026 results exhibit", "url": "https://www.sec.gov/Archives/edgar/data/1791706/000110465926067465/tm2615887d1_ex99-1.htm", "state": "official" } ], "unknowns": [ "compute architecture, precision-specific performance, and power", "process node, foundry, and lithography route", "memory type, capacity, supplier, and bandwidth", "package, assembly, and test path", "independent customer qualification and safety validation", "delivered Li L9 count using M100", "chip shipment and production volume", "yield and field reliability", "country-of-origin share" ], "entity_level_evidence_state": "derived", "entity_level_was_inferred": false, "entity_level_evidence_boundary": "This is a Touchdown-derived record-level category for comparing product families. It does not establish die count, package construction, supplier, manufacturing origin, qualification, shipment volume, or deployment scale.", "accelerator_type_state": "derived", "accelerator_type_was_inferred": false, "accelerator_type_boundary": "This is a Touchdown-normalized accelerator category based on the record's stated role and architecture. It does not establish undocumented microarchitecture, instruction compatibility, software parity, workload performance, or manufacturing relationships.", "software_evidence_boundary": "The named software list is normalized from the product record's reviewed source set. It does not prove that every component supports every product variant, operator, framework version, workload, deployment mode, or production reliability requirement." } ], "manufacturing_watch": [ { "id": "china-domestic-immersion-duv", "subject": "China-developed immersion-DUV scanner", "state": "reported", "status": "Initial low-rate production reported; customer qualification and high-volume fab use not publicly established", "current_claim": "The Information, relayed by Reuters on July 27, 2026, reported initial production with targets of roughly five systems in 2026 and twenty in 2027.", "not_proven": [ "completed and accepted systems", "complete disclosed bill of materials", "qualified production insertion", "overlay and CDU at production", "throughput and uptime", "electrical yield", "high-volume chip production" ], "source": "https://live.euronext.com/en/financial-news/china-begins-making-homegrown-duv-chipmaking-tools-information-reports" }, { "id": "china-euv", "subject": "China-developed EUV scanner", "state": "reported", "status": "Prototype work reported; no public wafer-imaging, working-chip, qualified-production, or commercial scanner receipt", "current_claim": "Public reporting supports at most an early prototype that generated EUV light.", "not_proven": [ "production wafer imaging", "working chips", "qualified fab insertion", "commercial shipment", "high-volume manufacturing" ], "source": "https://www.theinformation.com/briefings/china-builds-prototype-key-chip-manufacturing-machine/" } ], "model_memory_examples": [ { "parameters": "6T", "format": "BF16", "bytes_per_parameter": 2, "minimum_weight_tb": 12, "note": "Weights only; excludes KV cache, activations, workspace, replication, fragmentation, and serving concurrency." }, { "parameters": "6T", "format": "INT8", "bytes_per_parameter": 1, "minimum_weight_tb": 6, "note": "Weights only; quantization metadata and runtime state add capacity." }, { "parameters": "6T", "format": "4-bit", "bytes_per_parameter": 0.5, "minimum_weight_tb": 3, "note": "Weights only; actual packed formats and scaling metadata vary." } ], "publication_boundary": "This atlas compares public evidence, not private benchmark access. Company specifications stay labeled as claims; missing values stay unknown. No product is declared equivalent to H200, Blackwell, or Rubin without a matched workload, quality, latency, power, system, and cost receipt.", "product_packet_boundary": "A normalized product record establishes only the fields attributed to its listed sources. It does not close the candidate's supplier, qualification, yield, shipment-volume, or country-of-origin gates.", "source_packets": [ { "path": "./product-packets/china-expansion-a-v1.json", "sha256": "f772aee9816d9aed5df01f72113c7662e81994cc4bf67196b22a71fd94c35428", "product_count": 7 }, { "path": "./product-packets/china-expansion-b-v1.json", "sha256": "b671b16480ab2cb93bc20a8e4c9a18939ca7283955ee2a29f727e316ebe41173", "product_count": 9 }, { "path": "./product-packets/china-expansion-c-v1.json", "sha256": "237ba837a6659103f53612c9ffe38db91adabaaab380d5cc5432a1a712845617", "product_count": 7 } ], "candidate_reconciliation": { "ledger": "./candidate-ledger-v1.json", "promoted_candidate_ids": [ "candidate-cn-alibaba-t-head-hanguang", "candidate-cn-allwinner-client-edge-npu", "candidate-cn-axera-edge-automotive-ai-socs", "candidate-cn-black-sesame-huashan-wudang", "candidate-cn-corerain-dataflow", "candidate-cn-denglinai-gpgpu", "candidate-cn-hygon-dcu", "candidate-cn-innosilicon-graphics-compute", "candidate-cn-intellifusion-ai-accelerators", "candidate-cn-jingjia-micro-graphics-compute", "candidate-cn-li-auto-automotive-silicon", "candidate-cn-lisuan-graphics", "candidate-cn-nio-automotive-silicon", "candidate-cn-rockchip-client-edge-npu", "candidate-cn-sophgo-bitmain-ai-accelerators", "candidate-cn-tencent-zixiao", "candidate-cn-tsingmicro-reconfigurable-ai", "candidate-cn-unisoc-client-edge-ai", "candidate-cn-vastai-ai-accelerators", "candidate-cn-xpeng-automotive-silicon" ], "promoted_candidate_count": 20, "base_product_count": 15, "expansion_product_count": 23, "total_product_count": 38 } }