What can it run now?
Compare a named workload at the same quality, precision, software, system size, power boundary, latency, throughput, reliability, availability, and cost.
Start here · China first
One product. Fifteen gates. Three different questions.
Begin with a China-designed accelerator and follow it from the company that designed it to software, fabrication, DUV or EUV lithography, memory, packaging, systems, and qualified deployment. Then compare a U.S.-designed product across the same fifteen gates. This keeps technical progress, current workload performance, and supply-chain readiness from being collapsed into one score.
Why memory is in the center of this map
AI chips spend much of their time moving model data, not just calculating. If memory and interconnect cannot feed compute fast enough, headline TFLOPS sit idle. If fabrication, packaging, software, power, or qualification is missing, the product cannot ship as a usable system.
The complete product path
Every chip must cross these fifteen evidence gates.
A filled product fact is not automatically a named supplier relationship. A company elsewhere in the census is not automatically part of this product. Unknown means the public receipt is missing—not that the stage does not exist.
- 01Design companyWho owns the product record?
- 02Architecture & IPWhat compute design and reusable blocks?
- 03EDAWhich design and verification tools?
- 04Logic fab & processWhich foundry, line, node, and yield?
- 05DUV / EUV lithographyWhich scanners, masks, resist, and patterning flow?
- 06Wafer equipmentWhich deposition, etch, clean, CMP, and metrology tools?
- 07Critical materialsWhich wafers, gases, targets, slurries, and chemicals?
- 08MemoryWho makes the DRAM, HBM, NAND, or alternative memory?
- 09PackageWho integrates logic, memory, interposer, and substrate?
- 10Assembly & testWho bonds, tests, bins, and qualifies known-good parts?
- 11Board & systemWho builds the card, server, or rack?
- 12NetworkingHow does data move between chips and systems?
- 13Power & coolingWhat keeps the system operating at useful throughput?
- 14Software & workloadCan real models run with usable quality and reliability?
- 15Qualification & volumeWhat proves repeatable production and deployment?
Static, indexable evidence view: inspect 38 China and 17 U.S. products across all fifteen stages without JavaScript. The roster preserves 55 known, 350 partial, and 420 unknown product-fact states and keeps named supplier relationships separate.
The product comparison is one layer. The master supply-chain census is larger.
The accelerator registry compares normalized products. This dated universe separately accounts for every research seed across chip design, EDA, fabs, DUV and EUV patterning, equipment, materials, memory, packaging, boards, systems, networking, power, cooling, software, deployment, and demand. A seed is an investigation target—not proof that a company has a capability or supplies a named chip.
239unique dated names and research queues
304placements across sixteen supply-chain queues
135canonical entity resolutions
9crosswalk candidates to review
95still need primary research
Who exists at each stage?
The census below shows the full research queue and the canonical company records already resolved. It never turns category membership into a supplier claim.
What is known for one product?
The 15-stage map below shows product facts and named product-to-supplier relationships. Everything else stays unknown until a source connects the exact product and company.
Open the product-specific map →Sixteen supply-chain queues
Start with a stage, then open the exact company or research seed.
Counts can appear in more than one category because the same company may design chips, operate a fab, supply memory, or buy systems. The unique-universe total is deduplicated.
Loading the dated master universe…
Coverage boundary: this is a dated research universe, not a timeless claim to every company in China. New discoveries must be added with a source and disposition. Resolved identity still does not prove a product-specific supplier, customer, facility, qualification, volume, or deployment relationship.
Open the complete indexable 239-name roster → Works without JavaScript and preserves all sixteen category placements.
Open the typed industrial registry1,039 typed records · 15 stages · 63 tools · 61 materials · 33 facilities · 101 canonical relationships · 0 inferred edges
From company names to exact industrial records
See the products, factory tools, materials, facilities, processes, dependencies, and missing receipts behind the graph.
For an investor, this shows where public industrial evidence is dense or thin. For an executive, it separates a possible vendor from a source-backed product or facility. For an engineer, every card preserves the canonical fields, exact model or portfolio boundary, readiness, unknowns, and source trail.
1,039typed records
217companies and identity records
92products and service records
63factory tools
61materials
101canonical relationships
199explicit missing receipts
The 15-stage industrial path
Choose one stage. Then inspect the exact record.
The same record may appear in more than one stage because one company, tool, material, or relationship can cover multiple process steps. Counts are typed placements, not market share, output, matched technical performance, or complete supply-chain coverage.
Loading the typed industrial registry…
Complete accounting, incomplete research: the endpoint accounts for every record in the dated canonical datasets. It does not claim that every Chinese semiconductor company, product, tool, material, facility, or relationship has been discovered.
Open the 23-step workload-to-production explanationPlain-language decision first · engineering detail underneath · one China design compared with one U.S. design
Walk from the workload to the production receipt in 23 steps.
Choose one China-designed system and one U.S.-designed system. Each step gives the plain-language decision first, the engineering question underneath it, the exact product record, its evidence state, and what the public record still does not prove.
Performance and production evidence stay separate.
First ask whether the product completes the workload. Then ask which design, manufacturing, supply, qualification, and production-scale gates have source-backed progress. A milestone advances one gate; it does not establish matched workload performance or repeatable volume.
Step 01 of 23
Job to complete: workload
Investor and executive meaning
Engineering check
Loading the comparison data…
If the interactive view does not load, open the registry endpoint.
Step 1 of 23
Conceptual diagram—not to scale. Country identifies the design company’s headquarters, not the origin of every die, memory stack, package, board, tool, or material. Product-specific suppliers remain unknown unless a named relationship is sourced.
See how each AI accelerator is made, connected, and used.
Choose a path and a stage. The map shows every recorded company, product family, or dependency in that part of the chain, labels geography only to the level established by the source record, and opens the exact relationships and missing receipts behind the node. Product records use design-company headquarters. Capability records may use a source-recorded ownership country. Unresolved geography stays unknown. A Chinese or U.S. chip can still depend on Taiwan, South Korea, Japan, the Netherlands, another country, or an unresolved supplier.
How to read this:
Product performance, supply-chain evidence, and rate of progress are three different questions. Progress at one stage is not matched workload performance. A benchmark is not production proof.
Showing the China supply chain first. Source-backed global dependencies and unresolved product links remain visible.
Selected China or comparison product path
What is confirmed from product to production?
Each stage separates two questions: what we know about the product, and whether a product-specific supplier relationship is actually sourced. Known or partial product detail never becomes a supplier guess.
●Known
◐Partial product fact
?Unknown
—Not applicable
Loading the selected China and U.S. product-path records…
Select any China or U.S. stage to read its recorded state and unresolved boundary.
Conceptual diagram—not to scale. The sequence shows required coverage categories. It does not draw a supplier edge unless the endpoint contains that relationship.
Browse all capabilities
Now inspect the companies and dependencies recorded at each layer.
This broader census provides context. A company appearing here is not proof that either selected product uses it.
Coverage boundary
The China lane shows the canonical records that match the selected stage. Explicit gaps and records awaiting a clean stage classification remain accounted for in the typed industrial registry; they are not forced into a misleading graph position. The U.S. side is an anchor comparison, not an equally complete supplier census. A company appearing in a stage proves a recorded capability; it does not prove that NVIDIA, AMD, Huawei, DFSX, or another named designer buys from it.
Coverage is asymmetric.
The current combined graph totals are published in supply-chain-v1.json. Canonical supply-chain relationships are counted separately from product-to-design-company associations and unresolved product paths. The current U.S. anchor totals are published in us-supply-chain-v2.json. These counts measure research coverage, not market share, industrial capacity, or complete supply-chain coverage.
—authoritative graph nodes in the main endpoint
—canonical sourced relationships
—unresolved product-specific paths
—explicit research gaps
Conceptual diagram—not to scale. A solid relationship is source-backed. A dashed relationship is reported. A dotted outline marks an unresolved or explicitly unknown link. No product-to-supplier edge is inferred from technical fit.
Official The named primary source makes the claim.
Independent A third party directly tested, measured, or verified it.
Corroborated More than one named party supports it, without independent testing.
Reported A publication or vendor attributes the claim.
Derived Touchdown calculated or classified it from cited inputs.
Unknown The public record does not establish it.
CN
China lane
recorded design HQ / ownership country0records visible
US
United States lane
recorded design HQ / ownership country0records visible
GL
Other sourced geographies
recorded geography outside China and the United States0records visible
?
Unresolved product links
unknown owner or missing edge0records visible
U.S. reference paths, separated by physical level.
NVIDIA and AMD records below are normalized at the individual accelerator or rack-system level. Per-accelerator memory and bandwidth must not be compared with a 72-GPU rack aggregate. These are product facts and vendor readiness claims; they are not matched-workload results or proof of a fully U.S.-origin supply chain.
NVIDIA GPU acceleratorIndividual Blackwell accelerator packages with HBM3e
NVIDIA rack-scale system72 GPUs, 36 CPUs, fabric, power, cooling, trays, and software
NVIDIA next rack platformDisclosed future configuration with preliminary specifications
AMD Instinct acceleratorIndividual accelerators; memory figures use the per-accelerator denominator
Use the same denominator.
Accelerator-to-accelerator: B200, B300, MI300X, MI325X, MI350X, and MI355X. Rack-to-rack: GB200, GB300, and Vera Rubin NVL72. First match the physical level, model, precision, software, system size, power, cooling, latency, throughput, reliability, availability, and cost. Then inspect the supplier path.
U.S. capability lens: The bounded U.S. view shows source-backed design, software, manufacturing, integration, and deployment claims, global supplier contributions, and the receipts still needed to assess capacity and supply resilience. It remains a reference view, not a complete U.S. supplier census.
Open the seven-layer conceptual hardware schematicWorkload → software → rack → board → package → memory → process · not to scale
Take the machine apart, one layer at a time.
Choose one Chinese accelerator and one U.S. accelerator. Then move from the user’s workload down through software, rack, board, package, memory, and process. These are conceptual diagrams—not to scale—and unknown topology stays unknown instead of being presented as a sourced product drawing.
Layer 1 of 7 · Workload
Explore every tracked family on the company graphCurrent family total from the merged datasets · country → company → product · source trail and open coverage ledger
Now place every tracked family on the map.
This is a product-family map, not a logo wall and not a claim that every chip is made entirely in one country. “China” and “United States” identify the design company’s headquarters. Wafer fabrication, memory, packaging, assembly, equipment, and materials are separate fields—and stay unknown when the public evidence does not establish them.
—families tracked
—companies tracked
—accelerator types
—source links
TFLOPS is one ceiling, not the answer.
A chip with fewer arithmetic units can still win a bounded inference job if it keeps the units fed, avoids copies, matches the model, and scales cleanly. It cannot ignore compute. The complete path is what matters.
- 01Precision and sparsity
- 02Usable memory capacity
- 03Sustained bandwidth
- 04Collective topology
- 05Compiler and operators
- 06Workload throughput
- 07Power and system cost
Touchdown view: Compare two clocks. First, can the product complete the named workload at the required quality, cost, latency, power, and reliability? Second, how quickly is the path moving from design to qualified supply and deployed use? A product can be useful before it matches every reference metric. Its power, cooling, software, cost, reliability, and scale penalties still have to be counted.
Open the full product-card registryFilter the families in the current merged datasets by country, memory path, process class, and evidence state
China and U.S. accelerator registry
Every blank is deliberate. Open each card for the source trail, evidence state, and the exact fields still needed before making a stronger claim.
Loading product families…
CXMT LPDDR6: a reported validation milestone, not production proof.
A report surfaced on August 1 saying CXMT was close to completing LPDDR6 development validation. If confirmed, the important point is the time between readiness gates: joining an early cohort of a memory generation is materially different from arriving later. But “close to validation” remains upstream of customer qualification, yield, mass production, volume shipment, and a complete qualified supply path.
Current evidence state: reported. The supplied screenshot attributes the claim to Yicai and an unnamed industry source. The endpoint records the missing receipts explicitly: original article, CXMT statement, qualification evidence, production start, shipment volume, and yield.
The page and the endpoints use the same registry.
Start with the stable registry endpoint. It points to the 239-seed master research universe, the merged China and U.S. product datasets, the static 55-product path roster, both supply-chain endpoints, modular packet provenance, milestone events, and narrower candidate ledgers. That makes every dated seed, resolution state, source, and missing receipt downloadable without scraping the page.
registry.jsonStable entry point and current dataset manifest
product-paths/Indexable, no-JavaScript roster of 55 products × 15 stages: 55 known, 350 partial, and 420 unknown cells
coverage-universe-v3.htmlIndexable human-readable roster of every dated name, state, next receipt, and category placement
coverage-universe-v3.jsonAll 239 dated supply-chain seeds, canonical resolutions, crosswalk candidates, and unresolved research queues
industrial-registry-v1.json1,039 typed companies, products, tools, materials, facilities, processes, dependencies, relationships, and explicit gaps
data-v2.jsonMerged China product records, packet checksums, and candidate reconciliation
candidate-ledger-v1.jsonNarrower accelerator-product expansion ledger and open evidence gates
supply-chain-v1.jsonCompanies, sourced relationships, claims, sources, gaps, and manufacturing layers
us-supply-chain-v2.jsonU.S. and cross-border capability anchors with references to the authoritative product paths
us-data-v2.jsonNormalized, versioned U.S. product-family records
events-v1.json38 dated, source-bounded milestones across 28 exact products: 26 China events and 12 U.S. reference events, each held at its stated readiness gate
coverage-v2.jsonAccelerator-product inclusion scope, jurisdiction boundaries, and completeness limits
Three comparisons people get wrong
These rules keep mature-node and HBM-free designs interesting without letting the architecture story outrun the evidence.
14 nm does not “equal” 4 nm
A mature node can trade die area, specialization, 3D integration, memory locality, and more system scale for less transistor density. It may win a specific job. It usually pays somewhere in power, cooling, package complexity, yield, or total hardware.
HBM-free is not memory-free
DF1000 puts DRAM over logic. MLU370 and Journey 6 use LPDDR. Other designs may use conventional graphics memory. Each path still needs enough capacity, useful bandwidth, latency, RAS, and software support for the workload.
Aggregate links hide topology
A rack-level number is not per-peer bandwidth. Direction, ports, hops, oversubscription, bisection, congestion, collectives, and software scheduling decide how much data reaches the next chip on time.
A 6-trillion-parameter model does not always require 20 TB.
The number depends on representation and serving state. Twenty terabytes can be plausible after KV cache, activations, workspace, replicas, fragmentation, and concurrent long-context requests—but it is not a universal weight requirement.
minimum weight bytes ≈ parameter count × bytes per parameter
6T parameters at BF16 ≈ 12 TB of weights
6T parameters at INT8 ≈ 6 TB of weights
6T parameters at 4-bit ≈ 3 TB of packed weights
then add:
KV cache + activations + runtime workspace + quantization metadata
+ communication buffers + fragmentation + replication + concurrencyDUV production is progressing. Qualification is still the receipt.
On July 27, reporting said a China-based immersion-DUV program had entered initial production, targeting roughly five systems in 2026 and twenty in 2027. That is a dated readiness milestone. It does not yet prove accepted scanners, a complete bill of materials, production-line insertion, uptime, overlay, electrical yield, or high-volume chip production. Public EUV evidence remains earlier still.
What closes the claim: named scanner and fab, completed and accepted systems, overlay and critical-dimension uniformity, wafer throughput, uptime and service intervals, production lots, electrical yield, repeatable qualified use, and a disclosed component boundary. Until then, “initial production reported” is accurate; “complete, qualified high-volume production” is not.